Chenming Hu

Publications

Books

  1. C. Hu, R.M. White, “Solar Cells — from Basics to Advanced Systems,” McGraw-Hill, New York, 267 pages, 1983.
  2. Y. Cheng, C. Hu, “MOSFET Modeling and BSIM3 User Guide,” Kluwer Academic Publishers, 465 pages, 1999.
  3. C. Hu, “Modern Semiconductor Devices for Integrated Circuits,”  Pearson/Prentice Hall, New Jersey, 351 pages, 2010.
  4. W. Liu. C. Hu,”BSIM4 and MOSFET Modeling for IC Simulation,” World Scientific Publishing, Singapore, 414 pages, 2011.
  5. Y.S. Chauhan, D.D. Lu, V. Sriramkumar, S. Khandelwal, J. P. Duarte, N. Payvadosi, A. Niknejad, C. Hu,” FinFET Modeling for IC Simulation and Design: Using the BSIM-CMG Standard,” Academic Press, 298 pages, 2015.
  6. C. Hu, S. Khandelwal, Y.S. Chauhan, T. Mckay, J. Watts, J. P. Duarte, P. Kushwaha, H. Agarwal “Industry Standard FDSOI Compact Model BSIM-IMG for IC Design”, 2019 Elsevier

Edited Work

  1. L. Kasprzak, E. Takeda, C. Hu, editors, Reliability, special issue of IEEE Trans. on Electron Devices, 375 pages, December 1988.
  2. C. Hu, editor, “Nonvolatile Semiconductor Memories — Trans. Technologies, Design, and Applications”, IEEE Press, New York, 479 pages, 1991.
  3. C. Hu, editor, VLSI Reliability, special issue of Proc. of the IEEE, 141 pages, May 1993.

Book Chapters

  1. C. Hu, “Hot Carrier Effects,” Chapter 3 of Advanced MOS Device Physics, N.G. Einspruch, Editor, Academic Press, 1989, pp. 119-160.
  2. C. Hu, “Devices and Technology Impact on Low Power Electronics,” Chapter 2 of Low Power Design Methodologies, J.M. Rabaey and M. Pedram, Editors, Kluwer Academic Publishers, 1996.
  3. H.C. Shin, C. Hu, “Plasma Processing Damage in SiO2,” Chapter 4.3 of Semiconductor Process Induced Damage, Realize, Inc., 1996 (Japanese).
  4. W. Liu, C. Hu, “BSIM3v3 MOSFET Model,” Chapter 1 of Silicon and Beyond–Advanced Device Models and Circuit Simulators, M.S. Shur, T.A. Fjeldly, Editors, World Scientific Publishing Co., pp. 1-31, 2000.
  5. Y.-C. Yeo, Q. Lu, C. Hu, “MOSFET Gate Oxide Reliability: Anode Hole Injection Model and its Applications,” Chapter 5 of Selected Topics in Electronics and Systems, Vol. 23, Oxide Reliability- A Summary of Silicon Oxide Wearout, Breakdown, and Reliability, D. J. Dumin, Editor, World Scientific Publishing Co., pp. 233-270, 2002.
  6. M. V. Dunga, C-H. Lin, A. Niknejad, C. Hu, “BSIM-CMG: A compact Model for Multi-gate Transistors,” Chapter 3 in FinFETs and Other Multi-Gate Transistors, J. P. Colinge, Ed., Springer Science+Business Media, LLC. New York, NY , pp.113-153, 2007.
  7. J.J. Chen, N.R. Milke, C. Hu, “Flash memory Reliability,” Chapter 11 in Nonvolatile Memory Technologies with Emphasis on Flash, Joe Brewer and Manzur Gill, Editors, IEEE Press Series on Microelectronic Systems, pp.445-579, 2008.

Articles

  1. . Hu, R.S. Muller, “A Resistive-Gated IGFET Tetrode,” IEEE Trans. on Electron Devices, Vol. ED-18, July 1971, pp. 418-425.
  2. M. Chang, C. Hu, J.R. Whinnery, “Light Amplification in a Thin Film,” Digest of Topical Meeting on Integrated Optics , Las Vegas, NV, February 1972, Paper THA3-1.
  3. M. Chang, C. Hu, J.R. Whinnery, “Light Amplification in Thin Films,” Applied Physics Letters, 1972, pp. 313-314.
  4. C. Hu, J.R. Whinnery, “A New Thermo-Optical Measurement Method and a Comparison with Other Methods,” Applied Optics, Vol. 12, 1973, pp. 72-79.
  5. M. Chang, T.K. Gustafson, C. Hu, “Observation of Anti-Stoke Fluorescence in Organic Dye Solutions,” IEEE Journal Quan. Elec., 1972, pp. 527-528.
  6. R. Jain, C. Hu, T.K. Gustafson, “Absorption Processes Associated with Anti-Stokes Fluorescence in Rhodamine B Solutions,” Journal of Applied Physics, July, 1973, pp. 3157-3161.
  7. C. Hu, J.R. Whinnery, “Applications of Liquid Crystals in Integrated Optics,” Digest of Conf. on Laser Engineering and Applications , Washington, D.C., 1973.
  8. C. Hu, J.R. Whinnery, N.M. Amer, “Optical Deflection in Thin Film Nematic Liquid Crystal Waveguides,” IEEE Journal of Quantum Electronics, Vol. QE-10, 1973, pp. 218-222.
  9. C. Hu, J.R. Whinnery, “Nematic Liquid Crystal Optical Waveguides,” Digest of Topical Meeting on Integrated Optics , New Orleans, January, 1973, Paper TUA6.
  10. C. Hu, J.R. Whinnery, “Field-Realigned Nematic Liquid Crystal Optical Waveguides,” IEEE Journal of Quantum Electronics, Vol. QE-10, 1973, pp. 556-562.
  11. C. Hu, “Electro-Optical Modulation in Polycrystalline Films,” NSF Optical Communication Systems Meeting , University of Illinois, November 1974, pp. 89-92.
  12. C. Hu, J.R. Whinnery, “Losses of a Nematic Liquid Crystal Waveguide,” Journal of Optical Society of America, Vol. 64, 1973, pp. 1424-1432.
  13. C. Hu, “Electro-Optical Modulation in Grain Oriented ZnO Films,” IEEE Journal of Quantum Electronics, Vol. QE-11, September, 1975, p. 64D.
  14. C. Hu, S. Kim, “Thin Film Dye Laser with Etched Cavity,” Appl. Phys. Letters, Vol. 29, November, 1976, pp. 582-583.
  15. C. Hu, “Field Controlled Light Scattering in Nematic Liquid Crystals,” Proc. of the IEEE , Vol. 64, December, 1976, pp. 1737-1738.
  16. C. Hu, K.J. Carney, “New Analysis of a Vertical-Junction High Voltage Solar Cell,” Journal of Applied Physics, Vol. 48, January 1977, pp. 442-444.
  17. C. Hu, J. Edelberg, “Analysis of Stripe Geometry Junction Silicon Solar Cells,” Solid State Electronics, Vol. 20, February, 1977, pp. 119-123.
  18. J.R. Whinnery, C. Hu, Y.S. Kwon, “Liquid Crystal Waveguides for Integrated Optics,” IEEE Journal Quantum Elec., Vol. QE-13, April, 1977, pp. 262-267.
  19. C. Hu, “Some Considerations of the Optical Components of Light Fired Thyristors,” Proc. of Light-Fired Thyristors Workshop , Elec. Power Research Inst., March, 1978.
  20. C. Hu, “Light Emitting Diode Charge Control Model and High Injection Effects,” Proc. IEEE, Vol. 66, May, 1978, pp. 599-601.
  21. C. Hu, C. Drowley, “Open Circuit Voltage of High Intensity Silicon Cells,” 13th Photovoltaic Specialist Conf. , Washington, D.C., June, 1978, pp. 786-790.
  22. C. Hu, “Determination of Nonuniform Diffusion Length and Electric Field in Semiconductors,” IEEE Trans. Electron Dev., Vol. ED-25, July, 1978, pp. 822-825.
  23. C. Hu, C. Drowley, “Determination of Diffusion Length and Surface Recombination Lifetime with Optical Excitation,” Solid State Elec., Vol. 21, July, 1978, pp. 965-968.
  24. C. Hu, “Optimum Doping Profile for Minimum Ohmic Resistance and High-Breakdown Voltage,” IEEE Trans. Electron Dev., ED-26, March, 1979, pp. 243-244.
  25. C. Hu, “A Parametric Study of Power MOSFET’s,” Proc. Power Electronics Specialists Conf., San Diego, June 1979, pp. 385-395.
  26. C. Hu, Y. Shim, T. Klein, L. Elroy, “Current Field Characteristics of Oxides Grown from Poly-Si,” Appl. Phys. Letters, July 15, 1979.
  27. C. Hu, W.G. Oldham, “Carrier Recombination Through Shallow Acceptors/Donors in Heavily Doped Silicon,” Appl. Phys. Letters, October 1979, pp. 636-639.
  28. C. Hu, D.Y. Joh, Y. Shim, T. Klein, “Electron Trapping in Poly-Si Grown Oxides,” Int’l Electron Devices Conf., Washington, D.C., December, pp. 229-232.
  29. C. Hu, “Lucky Electron Model of Channel Hot Electron Emission,” International Electron Devices Conf., Washington, D.C., December 1979, pp. 22-25.
  30. Y.S. Kim, C. Hu, C. Drowley, “A New Method of Measuring Lifetime and Surface Recombination Velocity,” 14th IEEE Photovoltaic Specialist Conf., San Diego, CA, January 1980, pp. 596-600.
  31. H.C. Hsieh, C. Hu, C. Drowley, “A New Method of Analyzing Silicon Solar Cells,” IEEE Trans. Electron Devices, April 1980, pp. 883-884.
  32. C. Hu, W. Ki, “Toward a Practical Computer Aid for Thyristor Circuit Design,” IEEE Power Electronics Specialist Conf., Atlanta, GA, June 1980, pp. 174-179.
  33. C. Hu, M. Model, “A Model of Power Transistor Tun-off Dynamics,” IEEE Power Electronics Specialist Conf., Atlanta, GA, June 1980, pp. 91-96.
  34. M-H Chi, C. Hu, “Errors in Threshold-Voltage Measurements of MOS Transistor for Dopant Profile Determinations,” Solid State Electronics, Vol. 24, 1981, pp. 313-316.
  35. C. Drowley, C. Hu, “Arsenic Implanted Si Layers Annealed Using a Xe Arc Lamp,” Applied Physics Letters, Vol. 38, June 1981, pp. 876-878.
  36. P. Ko, S. Tam, C. Hu, R.S. Muller, “Correlation Between Substrate and Gate Currents in MOSFETs,” IEEE Trans. Electron Devices, October 1981, pp. 1260-1261.
  37. M.S. Liang, C. Hu, “Electron Trapping in Very Thin Thermal Silicon Dioxides,” Tech. Digest of IEEE International Electron Devices Meeting, December 1981, pp. 396-399.
  38. P.K. Ko, R.S. Muller, C. Hu, “A Unified Model for Hot-Electron Currents in MOSFET’s,” Tech. Digest of IEEE International Electron Devices Meeting, December 1981, pp. 600-603.
  39. C. Hu, “Drift Collection of Alpha Generated Carriers and Design Implications,” IEEE International Solid State Circuit Conf., February 1982, pp. 18-19.
  40. C. Hu, “Alpha-Particles-Induced Field and Enhanced Collection of Carriers,” IEEE Electron Device Letters, EDL-3, February 1982, pp. 31-34.
  41. C.I. Drowley, C. Hu, T.I. Kamins, “A Model for Laser Melting of Polysilicon in Multilayer Structures,” Abstracts of 16th Electrochemical Society Annual Meeting , Montreal, Canada, May 1982, pp. 234-235.
  42. C. Chang, M. Liang, T.Y. Chiu, C. Hu, W.G. Oldham, “Charge Transport in Oxide, Nitrided Oxide, and Nitride Films,” IEEE VLSI Workshop , Hyannis, MA, May 1982.
  43. M. Chi, C. Hu, “Some Issues of Power MOSFETs,” Record of IEEE Power Electronics Specialist Conf., June 1982, pp. 392-399.
  44. X-B. Chen, C. Hu, “Optimum Doping Profile of Power MOSFET Epitaxial Layer,” IEEE Trans. Electron Devices, ED-29, June 1982, pp. 985-987.
  45. R. Kagen, M. Chi, C. Hu, “Improving Switching Power Supply Efficiency by Using MOSFET Synchronous Rectifiers,” Proc. Powercon 9 , July 1982, D-4, pp. 1-5.
  46. M. Chi, C. Hu, “Second Breakdown of Power MOSFET,” IEEE Trans. Electron Devices, August 1982, pp. 1287-1293.
  47. S. Tam, P.K. Ko, F.C. Hsu, C. Hu, R.S. Muller, “Hot-Electron Induced Excess Carriers in N-Channel MOSFETs,” IEEE Trans. Electron Devices, October 1982, p. 1703.
  48. F.C. Hsu, P.K. Ko, S. Tam, R.S. Muller, C. Hu, “Avalanche Breakdown of Short Channel MOSFET’s,” IEEE Trans. Electron Devices, October 1982, p. 1702.
  49. C.I. Drowley, C. Hu, “A Comparison of CW Laser and Electron-Beam Recrystallization of Polysilicon in Multilayer Structures,” IEEE Conf. on Beam Processing , October 1982.
  50. S. Tam, P.K. Ko, C. Hu, R.S. Muller, “Correlation Between Substrate and Gate Currents in MOSFETs,” IEEE Trans. Electron Devices, November 1982, pp. 1740-1744.
  51. F.C. Hsu, P.K. Ko, S. Tam, C. Hu, R.S. Muller, “An Analytical Breakdown Model for Short Channel MOSFETs,” IEEE Trans. Electron Devices, November 1982, pp. 1735-1740.
  52. M.S. Liang, Y.T. Yeow, C. Chang, C. Hu, R.W. Brodersen, “MOSFET Degradation Due to Stressing of Thin Gate Oxide,” Digest of 1982 International Elect. Devices Meeting , December 1982, pp. 50-53.
  53. F.C. Hsu, R.S. Muller, C. Hu, “Characteristics of Short-Channel MOSFET’s in the Breakdown Regime,” Digest of 1982 International Electron Devices Meeting , December 1982, pp. 282-285.
  54. S. Tam, F.C. Hsu, R.S. Muller, C. Hu, P.I. Ko, “Hot-Electron Induced Excess Carriers in MOSFET’s,” IEEE Electron Devices Letters, December 1982, pp. 376-378.
  55. K.W. Terrill, C. Hu, A.R. Neureuther, “Computer Analysis of the Significance of Surface Boundary Conditions on the Collection of Alpha-Induced Charge,” Solid State Electronics, January 1983, pp. 15-18.
  56. D.S. Kuo, C. Hu, M.H. Chi, “dV/dt Breakdown in Power MOSFET’s,” IEEE Electron Devices Letters, January 1983, pp. 1-2.
  57. C. Hu, S. Tam, F.C. Hsu, R.S. Muller, P.K. Ko, “Correlating the Channel Substrate, Gate and Minority-Carrier Currents in MOSFETs,” Digest of 1983 IEEE International Solid State Circuit Conf. (ISSCC) , February 1983, pp. 282-285.
  58. M.H. Chi, C. Hu, “An Intrinsic Power MOSFET Model,” Proc. of Powercon 10, March 1983, H-2, pp. 1-4.
  59. C. Chang, R.W. Brodersen, C. Hu, “Direct and Fowler-Nordheim Tunneling in Thin Gate Oxide MOS Structures,” Insulating Films on Semiconductors (INFOS83), J.F. Verweij, D.R. Walter (Eds.), Elsevier Science Publishers B.V. (North Holland), 1983, pp. 176-180.
  60. C. Chang, M.S. Liang, C. Hu, R.W. Brodersen, “Charge Tunneling and Impact on Thin Oxide Device Reliability,” Proc. of Electrochemical Society Meeting, San Francisco, CA., May 1983, pp. 609-610.
  61. F.C. Hsu, R.S. Muller, C. Hu, “A Simplified Model of MOSFETs in the Breakdown Mode,” IEEE Trans. Electron Devices, June 1983, pp. 571-576.
  62. S. Tam, F.C. Hsu, C. Hu, R.S. Muller, P. Ko, “Hot Electron Currents in Very Short Channel MOSFETs,” IEEE Electron Device Letters, July 1983, pp. 249-251.
  63. M.S. Liang, C. Chang, Y.T. Yeow, C. Hu, R.W. Brodersen, “Creation and Termination of Substrate Deep Depletion in Thin Oxide MOS Capacitors by Charge Tunneling,” IEEE Electron Devices Letters, EDL-4, No. 10, October 1983, pp. 350-352.
  64. S. Tam, F.C. Hsu, P.K. Ko, C. Hu, R.S. Muller, “Spatially Resolved Observation of Visible Light Emission from Si MOSFET’s,” IEEE Electron Device Letters, EDL-4, No. 10, October 1983, pp. 386-388.
  65. P.F. Byrne, N.W. Cheung, S. Tam, C. Hu, Y.C. Shih, J. Washburn, M. Strathman, “Megavolt Boron and Arsenic Implantation into Silicon,” Applied Materials Research Conf. on Beam Processing , Boston, Mass., October 1983.
  66. F.C. Hsu, R.S. Muller, C. Hu, P.K. Ko, “A Simple Punchthrough Model for Short-Channel MOSFET’s,” IEEE Trans. Electron Devices, ED-30, No. 10, October 1983, pp. 1354-1359.
  67. C. Chang, R.W. Brodersen, M.S. Liang, C. Hu, “Direct Tunneling in Thin Gate-Oxide MOS Structures,” IEEE Trans. on Electron Devices, ED-30, November 1983, pp. 1571-1572.
  68. Invited Paper, C. Hu, “Charge Tunneling, Trapping, Device Degradation in Thin SiO2,” 1983 IEEE Surfaces and Interfaces Specialists Conf ., Fort Lauderdale, Florida, December 1-3, 1983.
  69. Invited Paper, C. Hu, “Hot-Electron Effects in MOSFET’s,” Tech. Digest of 1983 IEEE International Electron Devices Meeting (IEDM), Washington, D.C., December 1983, pp. 176-181.
  70. C. Chang, M.S. Liang, C. Hu, R.W. Brodersen, “Carrier-Tunneling Related Phenomena in Thin Oxide MOSFET’s,” Tech. Digest of IEEE International Electron Devices Meeting (IEDM), Washington, D.C., December 1983, pp. 194-197.
  71. M.S. Liang, C. Chang, W. Yang, C. Hu, R.W. Brodersen, “Hot-Carriers Induced Degradation in Thin Gate Oxide MOSFET’s,” Tech. Digest of IEEE International Electron Devices Meeting (IEDM), Washington, D.C., December 1983, pp. 186-189.
  72. C.S. Jeng, T. Wong, B. Joshi, C. Hu, “High Temperature and Extended Endurance Characteristics of EEROM,” Tech. Digest of IEEE International Electron Devices Meeting (IEDM), Washington, D.C., December 1983, pp. 589-592.
  73. T.C. Ong, K.W. Terrill, S. Tam, C. Hu, “Photon Generation in Forward-biased Silicon PN Junctions,” IEEE Electron Device Letters, EDL-4, No. 12, December 1983, pp. 460-462.
  74. B.J. Sheu, C. Hu, “Modeling the Switch-Induced Error Voltage on a Switched Capacitor,” IEEE Trans. on Circuits and Systems, CAS-30, No. 12, December 1983, pp. 911-913.
  75. M.H. Chi, C. Hu, “The Operation of Power MOSFET in Reverse Mode,” IEEE Trans. on Electron Devices, Vol. ED-340, December 1983, pp. 1825-1828.
  76. K. Terrill, C. Hu, A.R. Neureuther, “Computer Analysis, on the Collection of Alpha-Generated Charge for Reflecting and Absorbing Surface Conditions Around the Collector,” Solid State Electronics, Vol. 27, January 1984, pp. 45-52.
  77. D. Giandomenico, D.S. Kuo, J. Choi, C. Hu, “Analysis and Prevention of Anomalous Oscillations in a Vertical Power MOSFET,” Proc. of Powercon 11, April 1984, Dallas, Texas, pp. H-4, 1-9.
  78. B.J. Sheu, D.L. Scharfetter, C. Hu, D.O. Pederson, “A Compact IGFET Charge Model,” IEEE Trans. Circuits and Systems, Vol. CAS-31, August 1984, pp. 745-748.
  79. S. Holland, I.C. Chen, C. Hu, T.P. Ma, “On Physical Models for Gate Oxide Breakdown,” IEEE Electron Device Letters, Vol. EDL-5, August 1984, pp. 302-305.
  80. B.J. Sheu, C. Hu, “Switch-Induced Error Voltage on a Switched Capacitor,” IEEE Journal of Solid State Circuits, Vol. SC-19, August 1984, pp. 519-525.
  81. S. Tam, P.K. Ko, C. Hu, “Lucky-Electron Model of Channel Hot Electron Injection in MOSFETs,” IEEE Trans. Electron Devices, Vol. ED-31, September 1984, pp. 1116-1125.
  82. K. Terrill, C. Hu, “Substrate Resistance Calculation for Latch-up Modeling,” IEEE Trans. Electron Devices, Vol. ED-31, September 1984, pp. 1152-1155.
  83. M.S. Liang, C. Chang, Y.T. Yeow, C. Hu, R.W. Brodersen, “MOSFET Degradation Due to Stressing of Thin Oxide,” IEEE Trans. Electron Devices, Vol. ED-31, September 1984, pp. 1238-1244.
  84. S. Tam, C. Hu, “Hot-Electron Induced Photon and Photo-Carrier Generation in Silicon MOSFETs,” IEEE Trans. Electron Devices, Vol. ED-31, September 1984, pp. 1264-1273.
  85. Invited Paper, C. Hu, “Trends in Switching Power Semiconductor Devices,” Proc. of 1984 International Electronic Devices and Materials Symp., Hsinchu, Taiwan, September 1984, pp. 105-110.
  86. B.J. Sheu, C. Hu, P.K. Ko, F-C. Hsu, “Source-and-Drain Series Resistance of LDD MOSFETs,” IEEE Electron Device Letters, Vol. EDL-5, September 1984, pp. 365-367.
  87. P.F. Byrne, N.W. Cheung, S. Tam, C. Hu, Y.C. Shih, J. Washburn, M. Strathman, “Megavolt Boron and Arsenic Implantation into Silicon,” Ion Implantation and Ion Beam Processing of Materials, G.K. Hubler, Ed., North-Holland Publishing Co., 1984, pp. 253-258.
  88. K.W. Terrill, P.F. Byrne, C. Hu, N.W. Cheung, “Complementary Metal-Oxide-Silicon Field-Effect Transistors Fabricated in 4 MeV Boron Implanted Silicon,” Applied Physics Letters, Vol. 45, November 1, 1984, pp. 977-979.
  89. K.W. Terrill, C. Hu, P.K. Ko, “An Analytical Model for the Channel Electric Field in MOSFETs with Graded-Drain Structure,” IEEE Electron Device Letters, Vol. EDL-5, November 1984, pp. 440-442.
  90. T.Y. Chan, P.K. Ko, C. Hu, “A Simple Method to Characterize Substrate Current in MOSFETs,” IEEE Electron Device Letters, Vol. EDL-5, December 1984, pp. 505-507.
  91. M.S. Liang, J.Y. Choi, P.K. Ko, C. Hu, “Characterization of Very Thin Gate MOS Devices,” Tech. Digest of 1984 IEEE International Electron Devices Meeting (IEDM), December 1984, pp. 152-155.
  92. P.K. Ko, S. Tam, C. Hu, S. Wong, C. Sodini, “Enhancement of Hot-Electron Currents in Graded-Gate-Oxide (GGO) MOSFETs,” Tech. Digest of 1984 IEEE International Electron Devices Meeting (IEDM), December 1984, pp. 88-91.
  93. K.W. Terrill, P.F. Byrne, H.P. Zappe, N.W. Cheung, C. Hu, “A New Method for Preventing CMOS Latch-up,” Tech. Digest of IEEE International Electron Devices Meeting (IEDM), December 1984, pp. 406-409.
  94. C. Hu, M-H Chi, V.M. Patel, “Optimum Design of Power MOSFETs,” IEEE Trans. on Electron Devices, Vol. ED-31, December 1984, pp. 1693-1700.
  95. B.J. Sheu, C. Hu, P.K. Ko, F-C. Hsu, “Reply to Comments on Source-Drain Resistance of LDD MOSFETs,'” IEEE Electron Device Letters, Vol. EDL-5, December 1984, p. 535.
  96. C. Chang, R.W. Brodersen, C. Hu, “Quantum Yield of Electron Impact Ionization in Silicon,” Journal of Applied Physics, Vol. 57, January 1985, pp. 302-309.
  97. C. Hu, S. Tam, F-C. Hsu, P.K. Ko, T.Y. Chan, K. W. Terrill, K. Terrill “Hot-Electron Induced MOSFET Degradation-Model, Monitor, Improvement,” IEEE Trans. Electron Devices, Vol. ED-32, February 1985, pp. 375-385 and IEEE Journal Solid-State Circuits, Vol. SC-20, February l985, pp. 295-305.
  98. I.C. Chen, S. Holland, C. Hu, “Electrical Breakdown in Thin Gate and Tunneling Oxides,” IEEE Trans. Electron Devices, Vol. ED-32, February 1985, pp. 413-422 and IEEE Journal Solid-State Circuits, Vol. SC-20, February l985, pp. 333-342.
  99. I.C. Chen, S. Holland, C. Hu, “A Quantitative Physical Model for Time-Dependent Breakdown in SiO2,” Proc. of IEEE 23rd International Reliability Physics Symp. (IRPS), March 1985, pp. 24-31.
  100. D.S. Kuo, J.Y. Choi, D. Giandomenico, C. Hu, S.P. Sapp, K.A. Sassaman, R. Bregar, “Modeling the turn-off characteristics of the bipolar-MOS transistor” IEEE Electron Device Letters, Vol. EDL-16, May 1985, pp. 211-214.
  101. B.J. Sheu, C. Hu, P.K. Ko, T.Y. Chan, “On the High-Frequency and High-Speed Characteristics of MOS VLSI Circuits,” 2nd International Symp. on VLSI Technology, Systems, and Applications, Taipei, Taiwan, May 1985, pp. 231-234.
  102. I.C. Chen, S. Holland, C. Hu, “Wearout of Thin Gate and Tunneling Oxides,” 2nd International Symp. on VLSI Technology, Systems, and Applications, Taipei, Taiwan, May 1985, pp. 310-314.
  103. D. Giandomenico, D-S Kuo, C. Hu, “Oscillations in Multichip Power MOSFETs,” Power Conversion and Intelligent Motion, Aug. l985, pp. 74-78.
  104. T.C. Ong, S. Tam, P.K. Ko, C. Hu, “Width Dependence of Substrate and Gate Currents in MOSFETs,” IEEE Trans. on Electron Devices, Vol. ED-32, September 1985, pp. 1737-1740.
  105. T.Y. Chan, P.K. Ko, C. Hu, “Dependence of Channel Electric Field on Device Scaling,” IEEE Electron Device Letters, Vol. EDL-6, October 1985, pp. 551-553.
  106. C. Hu, “A Model of Dielectric Breakdown,” 1985 Wafer Reliability Assessment Workshop Report, October 1985, pp. 19-34.
  107. Invited Paper, C. Hu, “Thin Oxide Reliability,” Tech. Digest of International Electron Devices Meeting (IEDM), Washington, D.C., December 1985, pp. 368-371.
  108. H.P. Zappe, R.K. Gupta, K.W. Terrill, C. Hu, “Floating Well CMOS and Latchup,” Tech. Digest of International Electron Devices Meeting (IEDM), Washington, D.C., December 1985, pp. 517-520.
  109. T.Y. Chan, A.Y. Wu, P.K. Ko, C. Hu, R.R. Razouk, “Asymmetrical Characteristics in LDD and Minimum-Overlap MOSFETs,” IEEE Electron Device Letters, Vol. ED-33, March 1986, pp. 18-19.
  110. M.S. Liang, J.Y. Choi, P.K. Ko, C. Hu, “Inversion-Layer Capacitance and Mobility of Very Thin Gate-Oxide MOSFETs,” IEEE Trans. on Electron Devices, Vol. ED-33, March 1986, pp. 409-413.
  111. J. Lee, K. Mayaram, C. Hu, “A Theoretical Study of Gate/Drain Offset in LDD MOSFETs,” IEEE Electron Device Letters, Vol. EDL-7, March 1986, pp. 152-154.
  112. I.C. Chen, S. Holland, C. Hu, “Hole Trapping and Breakdown in Thin SiO2,” IEEE Electron Device Letters, Vol. EDL-7, March 1986, pp. 164-167.
  113. J. Lee, I.C. Chen, S. Holland, Y. Fong, C. Hu, “Oxide Defect Density, Failure Rate and Screen Yield,” Digest of Tech. Papers, IEEE Symp. on VLSI Technology, San Diego, CA., May 1986, pp. 69-70.
  114. K. Mayaram, J. Lee, T.Y. Chan, C. Hu, “An Analytical Perspective of LDD MOSFETs,” Digest of Tech. Papers, IEEE Symp. on VLSI Technology, San Diego, CA., May 1986, pp. 61-62.
  115. K.K. Young, T.Y. Chan, C. Hu, W.G. Oldham, “Hole Trapping and Hot-Carrier Induced Device Instability in Thin Nitride/Oxide IGFETs,” Digest of Tech. Papers, IEEE Symp. on VLSI Technology, San Diego, CA., May 1986, pp. 65-66.
  116. S. Holland, C. Hu, “Correlation Between Breakdown Susceptibility in Thin Thermal Si02 with Process-Dependent Positive Charge Trapping,” Proc. of the 5th International Symp. on Silicon Materials Science and Technology, (H.R. Huff, T. Abe, B. Kolbsen, eds.), The Electrochemical Society, May 1986, pp. 470-483.
  117. W.S. Feng, T.Y. Chan, C. Hu, “MOSFET Drain Breakdown Voltage,” IEEE Electron Device Letters, Vol. EDL-7, July 1986, pp. 449-450.
  118. S. J. Hrinya, C. Hu, “Residential Time-of-Use Kilowatt-hour Meter,” Electric Power Systems Research, Vol. 11, No. 1, August 1986, pp. 13-23.
  119. S. Holland, C. Hu, “Correlation Between Breakdown and Process-Induced Positive Charge Trapping in Thin Thermal Si02,” Journal of the Electrochemical Society, Vol. 133, No. 8, August 1986, pp. 1705-1712.
  120. J. Lee, I.C. Chen, C. Hu, “Comparison Between CVD and Thermal Gate Oxide Dielectric Integrity,” IEEE Electron Device Letters, Vol. EDL-7, Sept. 1986, pp. 506-509.
  121. D.S. Kuo, C. Hu, “Optimization of Epitaxial Layers for Power Bipolar-MOS Transistor,” IEEE Electron Device Letters, Vol. EDL-7, Sept. 1986, pp. 510-512.
  122. A.T. Wu, T.Y. Chan, P.K. Ko, C. Hu, “A Source-Side Injection Erasable Programmable Read Only Memory (SI-EPROM) Device,” IEEE Electron Device Letters, Vol. EDL-7, Sept. 1986, pp. 540-542.
  123. I.C. Chen, S. Holland, K.K. Young, C. Chang, C. Hu, “Substrate Hole Current and Oxide Breakdown,” Applied Physics Letters, Vol. 49, Sept. 15, 1986, pp. 669-671.
  124. D-S Kuo, C. Hu, “Speed-Conductance Optimization for Power Bipolar-MOS Transistor,” Conf. Record, IEEE Industry Applications Society Meeting, Denver, Colorado, September 28-Oct 3,1986, pp. 396-403.
  125. Invited Paper, S. Holland, I.C. Chen, J. Lee, Y. Fong, K.K. Young, C. Hu, “Time-Dependent Breakdown of Thin Oxides,” Proc. of Electrochemical Society Symp. on Silicon Nitride and Silicon Dioxide Thin Insulating Films, San Diego, CA., October 1986, pp. 361-382.
  126. R.K. Gupta, I. Sakai, C. Hu, “Analysis of Latch-Up Holding Voltage for Shallow Trench CMOS,” IEEE Electronics Letters, Vol. 22, No. 23, Nov. 1986, pp. 1261-1263.
  127. I.C. Chen, S. Holland, C. Hu, “Oxide Breakdown Dependence on Thickness and Hole Current — Enhanced Reliability of Ultra Thin Oxides,” Tech. Digest of International Electron Devices Meeting (IEDM), Los Angeles, CA., Dec. 1986, pp. 660-663.
  128. Y. Fong, I.C. Chen, J. Lee, S. Holland, C. Hu, “Dynamic Stressing of Thin Oxides,” Tech. Digest of International Electron Devices Meeting (IEDM), Los Angeles, CA., Dec. 1986, pp. 664-667.
  129. A.T. Wu, T.Y. Chan, P.K. Ko, C. Hu, “A Novel High-Speed, 5-Volt Programming EPROM Structure with Source Side Injection,” Tech. Digest, IEEE International Electron Device Meeting (IEDM), Los Angeles, CA., Dec. 1986, pp. 586-589.
  130. H.J. Park, P.K. Ko, C. Hu, “A Measurement-Based Charge Sheet Capacitance Model of Short-Channel MOSFET’s for SPICE,” Tech. Digest, IEEE International Electron Device Meeting (IEDM), Los Angeles, CA., Dec. 1986, pp. 40-43.
  131. M.P. Brassington, R.R. Razouk, C. Hu, “Effects of PECVD Nitride Passivation and Post-Passivation Anneals on Device Degradation,” IEEE Surface and Interfaces Specialist Conf., Los Angeles, CA., Dec. 1986.
  132. Invited Paper, P.K. Ko, T.Y. Chan, A.T. Wu, C. Hu, “The Effects of Weak Gate-to-Drain (Source) Overlap on MOSFET Characteristics,” Tech. Digest of International Electron Device Meeting (IEDM), Los Angeles, CA, Dec. 1986, pp. 292-295.
  133. D.S. Kuo, C. Hu, S.P. Sapp, “An Analytical Model for the Power Bipolar-MOS Transistor,” Solid State Electronics, Vol. 29, No. 12, Dec. 1986, pp. 1229-1238.
  134. G. Chen, S. Sapp, N. Wylie, C. Hu, “A Novel Contact Process for Power MOSFETs,” IEEE Electron Device Letters, EDL-7, No. 12, December 1986, pp. 672-673.
  135. H.P. Zappe, C. Hu, “Device Characteristics of MOSFET’s in MeV Implanted Substrates,” Nuclear Instruments and Methods in Physics Research B21 (1987), North Holland Publishing, Amsterdam, 1987, pp. 163-167.
  136. H.P. Zappe, R.K. Gupta, I. Sakai, C. Hu, “Operation of CMOS Devices with a Floating Well,” IEEE Trans. Electron Devices, Vol. ED-34, February 1987, pp. 335-343.
  137. G. Samachisa, C-S Su, Y-S Kao, G. Smarandiou, T. Wong, C. Hu, “A 128K Flash EEPROM Using Double Polysilicon Technology,” IEEE International Solid-State Circuits Conf. (ISSCC) Digest of Tech. Papers, Feb. 1987, pp. 76-77.
  138. T.Y. Chan, K.K. Young, C. Hu, “A True Single Transistor Oxide-Nitride-Oxide EEPROM,” IEEE Electron Device Letters, EDL-8, No. 3, March 1987, pp. 93-95.
  139. J.Y. Choi, P.K. Ko, C. Hu, “Effect of Oxide Field on Hot-Carrier-Induced Metal-Oxide-Semiconductor Field-Effect Transistor Degradation,” Applied Physics Letters, Vol. 50, No. 17, Apr. 27, 1987, pp. 1188-1190.
  140. I.C. Chen, C. Hu, “Accelerated Testing of Time-Dependent Breakdown of SiO2,” IEEE Electron Device Letters, EDL-8, No. 4, Apr. 1987, pp. 140-142.
  141. K.K. Young, C. Hu, W.G. Oldham, “Charge Transport and Trapping Model for Scaled Nitride-Oxide Stacked Films,” Applied Surface Science, (North Holland Publishing, Amsterdam), Vol. 30, 1987, pp. 171-179.
  142. H. Tsai, L. Wu, C. Wu, C. Hu, “The Effects of Thermal Nitridation Conditions on the Reliability of Thin Nitrided Oxide Films,” IEEE Electron Device Letters, EDL-8, No. 4, Apr. 1987, pp. 143-145.
  143. Invited Paper, C. Hu, “Hot Electron Effects in VLSI MOSFETs,” Tech. Digest of 3rd International Symp. on VLSI Technology, Systems and Applications, Taipei, Taiwan, May 1987, pp. 79-84.
  144. I.C. Chen, S. Holland, C. Hu, “Electron Trap Generation and Defect in SiO2,” Proc. International Symp. on VLSI Technology, Systems and Applications, Taipei, Taiwan, May 1987, pp. 85-86.
  145. T.Y. Chan, K.K. Young, C. Hu, “An Oxide-Nitride EEPROM Device with One Transistor Per Bit,” Proc. International Symp. on VLSI Technology, Systems and Applications, Taipei, Taiwan, May 1987, pp. 251-254.
  146. A.T. Wu, T.Y. Chan, P.K. Ko, C. Hu, “Uniformity and Process Control of Gate Current Characteristics in Two Source-Side Injection EPROM Technologies,” Proc. International Symp. on VLSI Technology, Systems and Applications, Taipei, Taiwan, May 1987, pp. 246-250.
  147. T.Y. Chan, A.T. Wu, P.K. Ko, C. Hu, “Effects of the Gate-to-Drain/Source Overlap in MOSFET Characteristics and Its Impact on Submicron Technology,” Tech. Digest, 3rd International Symp. on VLSI Technology, Systems and Applications, Taipei, Taiwan, May 1987, pp. 101-105.
  148. I.C. Chen, S. Holland, C. Hu, “Electron Trap Generation by Recombination of Electrons and Holes in SiO2,” Journal of Applied Physics, Vol. 61, No. 9, May 1987, pp. 4544-4548.
  149. I.C. Chen, J. Lee, C. Hu, “Accelerated Testing of Silicon Dioxide Wearout,” Tech. Digest, Symp. on VLSI Technology, Karuizawa, Japan, May 1987, pp. 23-24.
  150. J.Y. Choi, P.K. Ko, C. Hu, “Hot-Carrier Induced MOSFET Degradation: AC versus DC Stressing,” Tech. Digest Symp. on VLSI Technology, Karuizawa, Japan, May 1987, pp. 45-46.
  151. P. George, K. Hui, P. Ko, C. Hu, “A GaAs MESFET Model for Circuit Simulation, Proc. IEEE Custom Integrated Circuits Conf., May 1987, pp. 409-412.
  152. T.Y. Chan, A.T. Wu, P.K. Ko, C. Hu, “A Capacitance Method to Determine the Gate-to-Drain/Source Overlap Length of MOSFETs,” IEEE Electron Device Letters, Vol. EDL-8, No. 6, June 1987, pp. 269-271.
  153. K. Mayaram, J. Lee, C. Hu, “A Model for the Electric Field in Lightly Doped Drain Structures,” IEEE Trans. on Electron Devices, Vol. ED-34, No. 7, July 1987, pp. 1509-1518.
  154. T.Y. Chan, A.T. Wu, P.K. Ko, C. Hu, “Effects of the Gate-to-Drain/Source Overlap on MOSFET Characteristics,” IEEE Electron Device Letters, Vol. EDL-7, No. 7, July 1987, pp. 326-328.
  155. J.Y. Choi, P.K. Ko, C. Hu, “Hot-Carrier-Induced MOSFET Degradation Under AC Stress,” IEEE Electron Device Letters, Vol. EDL-7, No. 8, August 1987, pp. 333-335.
  156. D. Burnett, C. Hu, A. Kapoor, D. Nguyen, C. Yang, “Modeling of the AC Impedance of the Polysilicon-Silicon Interface,” Proc. IEEE Bipolar Circuits and Technology Meeting, Sept. 1987, pp. 154-156.
  157. T.C. Ong, P.K. Ko, C. Hu, “Modeling of Substrate Current in P-MOSFETs,” IEEE Electron Device Letters, Vol. EDL-8, No. 9, Sept. 1987, pp. 413-416.
  158. Invited Paper, C. Hu, “An Engineering Characterization of Defect-Related Breakdown of SiO2,” Proc. of the First Workshop on Process-Related Electrically Active Defects in Semiconductor-Insulator Systems, Research Triangle Park, N.C., Sept. 1987, pp. 1-3.
  159. G. Samachisa, C.S. Su, Y.S. Kao, G. Smarandiou, C.Y.M. Wang, T. Wong, C. Hu, “A 128K Flash EEPROM Using Double-Polysilicon Technology,” IEEE Solid-State Circuits, Vol. SC-22, No. 5, Oct. 1987, pp. 676-683.
  160. Best Paper Award, Y. Fong, C. Hu, “The Effects of High Electric Field Transients on Thin Gate Oxide MOSFETs,” Proc. Electrical Overstress/Electrostatic Discharge Symp., Orlando, Florida, Oct. 1987, pp. 252-257.
  161. T.C. Ong, P.K. Ko, C. Hu, “50 Å Gate-Oxide MOSFET’s at 77K,” IEEE Trans. on Electron Devices, Vol. ED-34, No. 10, Oct. 1987, pp. 2129-2135.
  162. J. Chen, T.Y. Chan, I.C. Chen, P.K. Ko, C. Hu, “Sub-Breakdown Drain Leakage Current in MOSFETs,” IEEE Electron Device Letters, Vol. EDL-8, No. 11, Nov. 1987, pp. 515-517.
  163. R.K. Gupta, I. Sakai, C. Hu, “Effects of Substrate Resistances on CMOS Latch-Up Holding Voltage,” IEEE Trans. on Electron Devices, Vol. ED-34, No. 11, Nov. 1987, pp. 2309-2316.
  164. M.M. Kuo, K. Seki, P.M. Lee, J.Y. Choi, P.K. Ko, C. Hu, “Quasi-Static Simulation of Hot-Electron-Induced MOSFET Degradation Under AC (Pulse) Stress,” Tech. Digest of International Electron Devices Meeting (IEDM), Washington, D.C., Dec. 1987, pp. 47-50.
  165. T.Y. Chan, J. Chen, P.K. Ko, C. Hu, “The Impact of Gate-Induced Drain Leakage Current on MOSFET Scaling,” Tech. Digest of International Electron Devices Meeting (IEDM), Washington, D.C., Dec. 1987, pp. 718-721.
  166. M.C. Jeng, J. Chung, A.T. Wu, T.Y. Chan, J. Moon, G. May, P.K. Ko, C. Hu, “Performance and Hot-Electron Reliability of Deep-Submicron MOSFET’s,” Tech. Digest of International Electron Devices Meeting (IEDM), Washington, D.C., Dec. 1987, pp. 710-713.
  167. H.J. Park, P.K. Ko, C. Hu, “A Non-Quasistatic MOSFET Model for SPICE,” Tech. Digest of International Electron Devices Meeting (IEDM), Washington, D.C., Dec. 1987, pp. 652-655.
  168. Y. Fong, A.T. Wu, R. Moazzami, P.K. Ko, C. Hu, “Oxide Grown on Textured Single-Crystal Silicon for Low Programming Voltage Non-Volatile Memory Applications,” Tech. Digest of International Electron Device Meeting (IEDM), Washington, D.C., Dec. 1987, pp. 889-891.
  169. S. Holland, I.C. Chen, C. Hu, “Ultra-Thin Silicon-Dioxide Breakdown Characteristics of MOS Devices with n+ and p+ Polysilicon Gates,” IEEE Electron Device Letters, Vol. EDL-8, No. 12, Dec. 1987, pp. 572-575.
  170. M.P. Brassington, R.R. Razouk, C. Hu, “Localized Interface Trap Generation in SILO-Isolated MOSFET’s During PECVD Nitride Passivation,” IEEE Trans. on Electron Devices, Vol. ED-35, No. 1, Jan. 1988, pp. 96-100.
  171. I.C. Chen, J.Y. Choi, T.Y. Chan, T.C. Ong, C. Hu, “The Effect of Channel Hot-Carrier Stressing on Gate Oxide Integrity in MOSFET,” Proc. IEEE International Reliability Physics Symp., Monterey, CA., Apr. 1988, pp. 1-7.
  172. Best Paper Award, J. Lee, I.C. Chen, C. Hu, “Statistical Modeling of Silicon Dioxide Reliability,” Proc. of IEEE International Reliability Physics Symp., Monterey, CA., Apr. 1988, pp. 131-138.
  173. J. Chung, M.C. Jeng, J.E. Moon, A.T. Wu, T.Y. Chan, P.K. Ko, C. Hu, “Deep Submicron MOS Device Fabrication Using a Photoresist-Ashing Technique,” IEEE Electron Device Letters, Vol. EDL-9, No. 4, Apr. 1988, pp. 186-188.
  174. Y. Fong, A.T. Wu, P.K. Ko, C. Hu, “Oxides Grown on Textured Single-Crystal Silicon for Enhanced Conduction,” Applied Physics Letters, Vol. 52, No. 14, April 1988, pp. 1139-1141.
  175. T.C. Ong, K. Seki, P.K. Ko, C. Hu, “Hot-Carrier Induced Degradation in P-MOSFET’s Under AC Stress,” IEEE Electron Device Letters, Vol. 9, No. 5, May 1988, pp. 211-213.
  176. B-K. Liew, N.W. Cheung, C. Hu, “Effects of High Current Pulses on Integrated Circuit Metallization Reliability,” IEEE Intersociety Conf. on Thermal Phenomena in the Fabrication and Operation of Electronic Components, Los Angeles, May 1988, pp. 3-6.
  177. J. Lee, C. Hu, “LPCVD Thin Oxide Process,” Digest of VLSI Technology Symp., San Diego, May 1988, pp. 49-50.
  178. B-K. Liew, N.W. Cheung, C. Hu, “Electromigration Interconnect Failure Under Pulse Test Conditions,” Digest of Symp. on VLSI Technology, San Diego, May 1988, pp. 59-60.
  179. J. Lee, C. Hu, “Polarity Asymmetry of Oxides Grown on Polycrystalline Silicon,” IEEE Trans. on Electron Devices, Vol. ED-35, No. 7, July, 1988, pp. 1063-1070.
  180. M.M. Kuo, M. Seki, P. Lee, J.Y. Choi, P.K. Ko, C. Hu, “Simulation of MOSFET Lifetime Under AC Hot Electron Stress,” IEEE Trans. on Electron Devices, Vol. ED-35, No. 7, July 1988, pp. 1004-1011.
  181. H.P. Zappe, C. Hu, “Characteristics of CMOS Devices in High Energy Boron Implanted Substrates,” IEEE Trans. on Electron Devices, Vol. 35, No. 7, July 1988, pp. 1029-1034.
  182. T.C. Ong, M. Levi, P.K. Ko, C. Hu, “Recovery of Threshold Voltage After Hot Carrier Stressing,” IEEE Trans. on Electron Devices, Vol. 35, No. 7, July 1988, pp. 978-984.
  183. J. Lee, C. Hegarty, C. Hu, “Electrical Characteristics of MOSFETs Using Low-Pressure Chemical Vapor Deposited Oxide,” IEEE Electron Device Letters, Vol. EDL-9, No. 7, July 1988, pp. 324-327.
  184. D. Burnett, C. Hu, “Hot Carrier Effects in Polysilicon Emitter Bipolar Transistors,” Proc. IEEE Bipolar Circuits and Technology Meeting, October 1988, pp. 95-98.
  185. M.C. Jeng, P.K. Ko, C. Hu, “Modeling Deep-Submicrometer MOSFETs for Analog/Digital Circuit Simulations,” Abstracts of Semiconductor Research Council (SRC) TECHCON, October 1988, Dallas, Texas, pp. 178-181.
  186. Best Presentation Award, C. Hu, P.K. Ko, P. Lee, J. Lee, N. Cheung, B.K. Liew, “IC Reliability Prediction,” Abstracts of Semiconductor Research Council (SRC) TECHCON, October 1988, Dallas, Texas, pp. 240-243.
  187. B. Tien, C. Hu, “Determination of Carrier Lifetime from Rectifier Ramp Recovery Waveform,” IEEE Electron Device Letters, EDL-9, No. 10, October 1988, pp. 553-555.
  188. Keynote Address, C. Hu, “Oxide Time Dependent Breakdown Testing Model,” Wafer Level Reliability Workshop Report, Lake Tahoe, October 1988, pp. 1-26.
  189. K.K. Young, C. Hu, W.G. Oldham, “Transport and Trapping Characteristics in Thin Nitride-Oxide Stacked Films,” IEEE Electron Device Letters, EDL-9, No. 11, November 1988, pp. 616-618.
  190. C. Hu, “Reliability by Design,” Digest of Government Microcircuit Applications Conf., Las Vegas, Nevada, November 1988, pp. 381-384.
  191. I.C. Chen, J.Y. Choi, T.Y. Chan, C. Hu, “The Effect of Channel Hot Carrier Stressing on Gate Oxide Integrity in MOSFET,” IEEE Trans. on Electron Devices, Vol. 35, No. 12, December 1988, pp. 2253-2258.
  192. J. Lee, I.C. Chen, C. Hu, “Modeling and Characterization of Oxide Reliability,” IEEE Trans. on Electron Devices, Vol. 35, No. 12, December 1988, pp. 2268-2278.
  193. D. Burnett, C. Hu, “Modeling Hot-Carrier Induced Base Leakage in Polysilicon Emitter Bipolar Transistors,” IEEE Trans. on Electron Devices, Vol. 35, No. 12, December 1988, pp. 2238-2247.
  194. K.K. Hung, P.K. Ko, C. Hu, Y.C. Cheng, “Flicker Noise Characteristics of Advanced MOS Technologies,” Tech. Digest of International Electron Devices Meeting (IEDM), San Francisco, CA., December 1988, pp. 34-37.
  195. H. Park, P. Ko, C. Hu, “A Charge Conserving Non-Quasistatic MOSFET Model for SPICE Transient Analysis,” Tech. Digest of International Electron Devices Meeting (IEDM), San Francisco, CA., December 1988, pp. 110-113.
  196. M.C. Jeng, P.K. Ko, C. Hu, “A Deep Submicron MOSFET Model for Analog/Digital Circuit Simulations,” Tech. Digest of International Electron Devices Meeting (IEDM), San Francisco, CA., December 1988, pp. 114-117.
  197. P.M. Lee, M.M. Kuo, K. Seki, P.K. Ko, C. Hu, “Circuit Aging Simulator (CAS),” Tech. Digest of International Electron Devices Meeting (IEDM), San Francisco, CA., December 1988, pp. 134-137.
  198. J. Chung, M.C. Jeng, G. May, P.K. Ko, C. Hu, “Hot Electron Currents in Deep Submicron MOSFETs,” Tech. Digest of International Electron Devices Meeting (IEDM), San Francisco, CA., December 1988, pp. 200-203.
  199. M. Jeng, J. Chung, G. May, P. Ko, C. Hu, “Design Guidelines for Deep-Submicron MOSFETs,” Tech. Digest of International Electron Devices Meeting (IEDM), San Francisco, CA., December 1988, pp. 386-389.
  200. K. Mayaram, B. Tien, C. Hu, D. Pederson, “Simulation and Modeling for Soft Recovery of p-i-n Rectifiers,” Tech. Digest of International Electron Devices Meeting (IEDM), San Francisco, CA., December 1988, pp. 622-625.
  201. R. Moazzami, J. Lee, I. Chen, C. Hu, “Projecting the Minimum Acceptable Oxide Thickness for Time Dependent Dielectric Breakdown,” Tech. Digest of International Electron Devices Meeting (IEDM), San Francisco, CA., December 1988, pp. 710-713.
  202. Invited Paper, C. Hu, “Engineering Model of Defect Induced Oxide Breakdown,” Abstracts of 19th IEEE Semiconductor Interface Specialists Conf., San Diego, December 1988, pp. 85-86.
  203. J. Chung, M-C. Jeng, G. May, P.K. Ko, C. Hu, “Intrinsic Transconductance Extraction for Deep-Submicron MOSFETs,” IEEE Trans. Electron Devices, Vol. 36, No. 1, January 1989, pp. 140-142.
  204. J.Y. Choi, P.K. Ko, C. Hu, W. Scott, “Hot-Carrier Induced MOSFET Degradation — Oxide Charge versus Interface Traps,” Journal of Applied Physics, Vol. 65, No. 1, 1 January 1989, pp. 354-360.
  205. T.C. Ong, P.K. Ko, C. Hu, “Hot-Carrier Effects in Depletion-Mode MOSFETs,” Solid State Electronics, Vol. 32, No. 1, January 1989, pp. 33-36.
  206. P. George, P.K. Ko, C. Hu, “Modeling the Substrate Depletion Region for GaAs FETs Fabricated on Semi-Insulating Substrates,” Solid State Electronics. Vol. 32, No. 2, February 1989, pp. 165-168.
  207. P. George, P.K. Ko, C. Hu, “A GaAs MESFET Model for Circuit Simulation,” International Journal of Electronics, Vol. 66, No. 3, March 1989, pp. 379-397.
  208. H.J. Park, P.K. Ko, C. Hu, “A Non-Quasistatic MOSFET Model for SPICE — Transient Analysis,” IEEE Trans. on Electron Devices, Vol. 36. No. 5, March 1989, pp. 561-576.
  209. T.C. Ong, K. Seki, P.K. Ko, C. Hu, “P-MOSFET Gate Current and Device Degradation,” Proc. International Reliability Physics Symp., Phoenix, AZ, April 1989, pp. 178-182.
  210. Y. Fong, C. Hu, “Internal ESD Transients in Input Protection Circuits,” Proc. International Reliability Physics Symp., Phoenix, AZ, April 1989, pp. 77-81.
  211. Best Paper Award, J. Chung, M.C. Jeng, J.E. Moon, P.K. Ko, C. Hu, “Low-Voltage Hot Electron Degradation in Deep Submicrometer MOSFETs,” Proc. International Reliability Physics Symp., Phoenix, AZ, April 1989, pp. 92-97.
  212. B.K. Liew, N.W. Cheung, C. Hu, “Electromigration Interconnect Lifetime Under AC and Pulse DC Stress,” Proc. International Reliability Physics Symp., Phoenix, AZ, April 1989, pp. 215-219.
  213. S. Aronowitz, H.P. Zappe, C. Hu, “Interfacial Charge Modification Between SiO2 and Silicon,” Appl. Phys. Letters, Vol. 54, No. 14, April 3, 1989, pp. 1317-1319.
  214. P. George, P.K. Ko, C. Hu, “Simulating the Effects of Single-Event and Radiation Phenomena on GaAs MESFET Integrated Circuits,” Proc. IEEE Custom Integrated Circuits Conf., San Diego, CA., May 1989, pp. 9.7.1-9.7.4.
  215. J. Chen, T-Y. Chan, P.K. Ko, C. Hu, “Gate Current in Off-State MOSFET,” IEEE Electron Device Letters, Vol. 10, No. 5, May 1989, pp. 203-205.
  216. R. Moazzami, C. Hu, “An Oxide Burn-In Model,” Digest of VLSI Technology Symp., Kyoto, Japan, May 1989, pp. 77-78.
  217. T.C. Ong, P.K. Ko, C. Hu, “P-MOSFET Gate Current and Device Degradation,” Proc. of International Symp. on VLSI Technology, Systems and Applications, Taipei, Taiwan, May 1989, pp. 193-196.
  218. K.K Hung, P.K. Ko, C. Hu, Y.C. Cheng, “An Automated System for Measurement of Random Telegraph Noise in MOSFETs,” IEEE Transactions on Electron Devices, Vol. 36, No. 6, June 1989, pp. 1217-1219.
  219. S. Aronowitz, H.P. Zappe, C. Hu, “Effective Charge Modification Between SiO2 and Silicon,” Journal of the Electrochemical Society, Vol. 136, No. 8, August 1989, pp. 2368-2370.
  220. T.C. Ong, P.K. Ko, C. Hu, “EEPROM as an Analog Memory Device,” IEEE Trans. on Electron Devices, Vol. 36, No. 9, September l989, pp. 1840-1841.
  221. Keynote Address, C. Hu, “Submicron IC Reliability Research at Berkeley,” Proc. Electrical Overstress/Electrostatic Discharge Symp.,  New Orleans, Louisiana, September 1989, pp. 1-6.  Symposium Keynote
  222. Invited Paper, C. Hu, “Reliability Issues of MOS and Bipolar IC’s,” Proc. IEEE International Conf. on Computer Design (ICCD), Cambridge, MA, October 1989, pp. 438-442.
  223. Invited Paper, C. Hu, “Submicron Device Reliability Research,” Tech. Digest, International Conf. on VLSI and CAD (ICVC), Seoul, Korea, October 1989, pp. 425-429.
  224. R. Moazzami, J. Lee, C. Hu, “Temperature Acceleration of Time-Dependent Dielectric Breakdown,” IEEE Trans. on Electron Devices. , Vol. 36, No. 11, November 1989, pp. 2462-2465.
  225. B.K. Liew, N.W. Cheung, C. Hu, “Effects of Self-Heating on Integrated Circuit Metallization Lifetimes,” Tech. Digest of International Electron Devices Meeting (IEDM), Washington, D.C., December 1989, pp. 323-326.
  226. E. Rosenbaum, P.M. Lee, R. Moazzami, P.K. Ko, C. Hu, “Circuit Reliability Simulator — Oxide Reliability Module,” Tech. Digest of International Electron Devices Meeting (IEDM), Washington, D.C., December 1989, pp. 331-334.
  227. J. Chung, J. Chen, M. Levi, P.K. Ko, C. Hu, “The Effects of Off-Axis Substrate Orientation on MOSFET Characteristics,” Tech. Digest of International Electron Devices Meeting (IEDM), Washington, D.C., December 1989, pp. 633-636.
  228. C. Lau, C. Hu, E.J. McCluskey, “Research in Advanced Electronic System Reliability,” Naval Review, Vol. XLI, Three/1989, pp. 9-19.
  229. L.J. Palkuti, R.D. Ormond, C. Hu., J. Chung, “Correlation Between Channel Hot-Electron Degradation and Radiation-Induced Interface Trapping in MOS Devices,” IEEE Trans. on Nuclear Sciences, Vol. 36, No. 6, December 1989, pp. 2140-2146.
  230. P.M. Lee, P.K. Ko, C. Hu, “Relating CMOS Inverter Lifetime to DC Hot-Carrier Lifetime of NMOSFETs,” IEEE Electron Device Letters, Vol. 11, No. 1, January 1990, pp. 39-41.
  231. K.K. Hung, P.K. Ko, C. Hu, Y.C. Cheng, “Random Telegraph Noise of Deep-Submicron MOSFETs,” IEEE Electron Device Letters, Vol. 11, No. 2, February 1990, pp. 90-92.
  232. Y. Fong, A.T. Wu, C. Hu, “Oxides Grown on Textured Single-Crystal Silicon — Dependence on Process and Application of EEPROMs,” IEEE Trans. on Electron Devices, Vol. 37, No. 3, March 1990, pp. 583-590.
  233. K.K. Hung, P.K. Ko, C. Hu, Y.C. Cheng, “A Unified Model for the Flicker Noise in Metal-Oxide-Semiconductor Field-Effect Transistors,” IEEE Trans. on Electron Devices, Vol. 37, No. 3, March 1990, pp. 654-665.
  234. B.K. Liew, P. Fang, N.W. Cheung, C. Hu, “Reliability Simulator for Interconnect and Intermetallic Contact Electromigration,” Proc. International Reliability Physics Symp., New Orleans, LA, March 1990, pp. 111-118.
  235. D. Burnett, C. Hu, “Hot-Carrier Reliability of Bipolar Transistors,” Proc. 1990 International Reliability Physics Symp., New Orleans, LA, March 1990, pp. 164-169.
  236. S. Chiang, R. Wang, J. Chen, K. Hayes, J. McCollum, E. Hamdy, C. Hu, “Oxide Nitride-Oxide Antifuse Reliability,” Proc. International Reliability Physics Symp., New Orleans, LA, March 1990, pp. 186-192.
  237. R. Moazzami, C. Hu, W.H. Shepherd, “Electrical Conduction and Breakdown in Sol-Gel Derived PZT Thin Films,” Proc. International Reliability Physics Symp., New Orleans, LA., March 1990, pp. 231-236.
  238. K. Hui, C. Hu, P. George, P.K. Ko, “Impact Ionization in GaAs MOSFETs,” IEEE Electron Device Letters, Vol. 11, No. 3, March 1990, pp. 113-115.
  239. J.D. Burnett, C. Hu, “Hot-Carrier Degradation in Bipolar Transistors at 300 and 110 K-effect on BiCMOS Inverter Performance,” IEEE Trans. on Electron Devices, Vol. 37, No. 4, April 1990, pp. 1171-1173.
  240. K.K. Hung, P.K. Ko, C. Hu, Y.C. Cheng, “A Physics-Based MOSFET Noise Model for Circuit Simulators,” IEEE Trans. Electron Devices, Vol. 37, No. 4, May 1990, pp. 1323-1333.
  241. B.K. Liew, N. Cheung, C. Hu, “Projecting Interconnect Electromigration Lifetime for Arbitrary Current Waveforms,” IEEE Trans. on Electron Devices, Vol. 37, No. 5, May 1990, pp. 1343-1351.
  242. J.E. Moon, T. Garfinkel, J. Chung, M. Wong, P.K. Ko, C. Hu, “A New LDD Structure: Total Overlap with Polysilicon Spacer (TOPS),” IEEE Electron Device Letters, Vol. 11, No. 5, May 1990, pp. 221-223.
  243. R. Moazzami, C. Hu, W.H. Shepherd, “A Ferroelectric DRAM Cell for High Density NVRAMs,” Digest of Tech. Papers of Symp. on VLSI Technology, Honolulu, Hawaii, June 1990, pp. 15-16.
  244. P. Fang, K.K. Hung, P.K. Ko, C. Hu, “Characterizing a Single Hot-Electron-Induced Trap in Submicron MOSFET Using Random Telegraph Noise,” Digest of Tech. Papers of Symp. on VLSI Technology, Honolulu, Hawaii, June 1990, pp. 37-38.
  245. R. Moazzami, C. Hu, “Projecting Gate Oxide Reliability and Optimizing Burn-in,” IEEE Trans. on Electron Devices, Vol. 37, No. 7, July 1990, pp. 1643-1650.
  246. J. Chung, M-C. Jeng, J. Moon, P.K. Ko, C. Hu, “Low Voltage Hot Electron Degradation in Deep Submicron MOSFETs,” IEEE Trans. on Electron Devices, Vol. 37, No. 7, July 1990, pp. 1651-1657.
  247. T.C. Ong, P.K. Ko, C. Hu, “Hot-Carrier Current Modeling and Device Degradation in Surface Channel P-MOSFET,” IEEE Trans. on Electron Devices, Vol. 37, No. 7, July 1990, pp. 1658-1666.
  248. Y. Fong, C. Hu, “High-Current Snapback Characteristics of MOSFETs,” IEEE Trans. on Electron Devices, Vol. 37, No. 9, September 1990, pp. 2101-2103.
  249. P. George, K. Hui, P.K. Ko, C. Hu, “The Reduction of Backgating in GaAs MESFET’s by Impact Ionization,” IEEE Electron Device Letters, October 1990, pp. 434-436.
  250. R. Moazzami, W.H. Shepherd, C. Hu, “A Ferroelectric DRAM Cell for High Density NVRAM’s,” IEEE Electron Device Letters, October 1990, pp. 454-456.
  251. J. Chen, P. Fang, P.K. Ko, C. Hu, “Noise Overshoot at Drain Current Kink in SOI MOSFET,” Proc. IEEE SOS/SOI Technology Conf., Key West, Florida, October 1990, pp. 40-41.
  252. P. George, P.K. Ko, C. Hu, “Model for Photo-Induced Long Term Drain Current Transients in GaAs MOSFETs,” International Journal of Electronics, Vol. 68, No. 5, October 1990, pp. 721-728.
  253. H.P. Zappe, S. Aronowitz, C. Hu, “Oxide Implantation for Threshold Voltage Control,” Solid-State Electronics, Vol. 33, No. 11, November 1990, pp. 1447-1453.
  254. M.C. Jeng, J.E. Chung, P.K. Ko, C. Hu, “The Effects of Source/Drain Resistance on Deep Submicron Device Performance,” IEEE Trans. on Electron Devices, Vol. 37, No. 11, November 1990, pp. 2408-2410.
  255. J.E. Chung, M.C. Jeng, J.E. Moon, P.K. Ko, C. Hu, “Low-Voltage Hot-Electron Currents and Degradation in Deep-Submicrometer MOSFETs,” Vol. 37, No. 7, pp. 1651-1657, November 1990.
  256. D. Burnett, T. Horiuchi, C. Hu, “Bipolar Circuit Reliability Simulation,” Tech. Digest of IEEE International Electron Devices Meeting, San Francisco, CA., December 1990, pp. 181-184.
  257. R. Moazzami, C. Hu, W.H. Shepherd, “Endurance Properties of Ferroelectric PZT Thin Films,” Tech. Digest of IEEE International Electron Devices Meeting, December 1990, pp. 417-420.
  258. J.E. Chung, K.N. Quader, C.G. Sodini, P.K. Ko, C. Hu, “The Effects of Hot-Electron Degradation on Analog MOSFET Performance,” Tech. Digest of IEEE International Electron Devices Meeting, December 1990, pp. 553-556.
  259. J.E. Chung, M.C. Jeng, J.E. Moon, P.K. Ko, C. Hu, “Performance and Reliability Design Issues for Deep-Submicron MOSFET’s,” IEEE Trans. on Electron Devices, Vol. 38, No. 3, March 1991, pp. 545-554.
  260. J.E. Chung, J. Chen, P.K. Ko, M. Levi, C. Hu, “The Effects of Low-Angle Off-Axis Substrate Orientation on MOSFET Performance and Reliability,” IEEE Trans. on Electron Devices, Vol. 38, No. 3, March 1991, pp. 627-633.
  261. H.J. Park, P.K. Ko, C. Hu, “A Charge Sheet Capacitance Model of Short Channel MOSFET’s for SPICE,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 10, No. 3, March 1991, pp. 376-389.
  262. P. George, P.K. Ko, C. Hu, “The Influence of Substrate Compensation on Inter-Electrode Leakage and Back-Gating in GaAs MOSFETs,” Solid State Electronics, Vol. 34, No. 3, March 1991, pp. 233-252.
  263. H.J. Park, P.K. Ko, C. Hu, “A Charge Conserving Non-Quasi-Static MOSFET Model for SPICE Transient Analysis,” IEEE Computer Aided Design of Integrated Circuits and Systems, Vol. 10, No. 5, May 1991, pp. 629-642.
  264. Invited Paper, C. Hu, “IC Reliability Simulation,” Proc. IEEE Custom Integrated Circuits Conf., San Diego, May 1991, pp. 4.1.1-4.1.4.
  265. R. Moazzami, C. Hu, “A High Quality Stacked Thermal/LPCVD Gate Oxide for ULSI,” Proc. of Tech. Papers, 1991 International Symp. on VLSI Technology, Systems, and Applications, Taipei, Taiwan, May 1991, pp. 52-56.
  266. J.E. Moon, C. Galewski, T. Garfinkel, M. Wong, W.G. Oldham, P.K. Ko, C. Hu, “A Deep-Submicrometer Elevated Source/Drain LDD Structure Fabricated Using Hot-Wall Epitaxy,” Proc. Tech. Papers, 1991 International Symp. on VLSI Technology, Systems, and Applications, Taipei, Taiwan, May 1991, pp. 117-121.
  267. P.M. Lee, T. Garfinkel, P.K. Ko, C. Hu, “Simulation of P- and N-MOSFET Hot Carrier Degradation in CMOS Circuits,” Proc. of Tech. Papers, International Symp. on VLSI Technology, Systems, and Applications, Taipei, Taiwan, May 1991, pp. 191-195.
  268. H. Shin, R. Moazzami, C.C. King, C. Hu, T. Horiuchi, “Characterization of Thin Oxide Damage During Aluminum Etching and Photoresist Ashing Processes,” Proc. of Tech. Papers, International Symp. on VLSI Technology, Systems, and Applications, Taipei, Taiwan, May 1991, pp. 210-213.
  269. E. Rosenbaum, R. Moazzami, C. Hu, “Implications of Waveform and Thickness Dependence of SiO2 Breakdown on Accelerated Testing,” Proc. of Tech. Papers, International Symp. on VLSI Technology, Systems, and Applications, Taipei, Taiwan, May 1991, pp. 214-218.
  270. J. Chen, P.K. Ko, C. Hu, “Effects of the Field-Edge Transistor on SOI MOSFETs,” Proc. of Tech. Papers, International Symp. on VLSI Technology, Systems, and Applications, Taipei, Taiwan, May 1991, pp. 219-223.
  271. S. Parke, J. Moon, P. Nee, J. Huang, C. Hu, P.K. Ko, “Gate-Induced Drain Leakage in LDD and Fully-Overlapped LDD MOSFETs,” Symp. on VLSI Technology Digest of Tech. Papers, Oiso, Japan, May 1991, pp. 49-50.
  272. R. Moazzami, N. Akt, Y. Nissan-Cohen, W.H. Shepherd, M.P. Brassington, C. Hu, “Impact of polarization Relaxation on Ferroelectric Memory Performance,” Symp. on VLSI Technology Digest of Tech. Papers Oiso, Japan, May 1991, pp. 61-62.
  273. V. Jain, D. Pramanik, K.Y. Chang, C. Hu, “Improved Sub-Micron CMOS Device Performance Due to Fluorine in CVD Tungsten Silicide,” Symp. on VLSI Technology Digest of Tech. Papers, Oiso, Japan, May 1991, pp. 91-92.
  274. Invited Paper, P.M. Lee, P.K. Ko, C. Hu, “Circuit Reliability Simulation: An Overview,” Proc. of International Workshop on VLSI Process and Device Modeling (VPAD), Oiso, Japan, May 1991, pp. 130-133.
  275. J.E. Chung, P.K. Ko, C. Hu, “A Model for Hot-Electron-Induced MOSFET Linear-Current Degradation Based on Mobility Reduction Due to Interface State Generation,” IEEE Trans. on Electron Devices, Vol. 38, No. 6, June 1991, pp. 1362-1370.
  276. E. Rosenbaum, C. Hu, “High-Frequency Time-Dependent Breakdown of SiO2,” IEEE Electron Device Letters, Vol. 12, No. 6, June 1991, pp. 267-269.
  277. P. Fang, K.K. Hung, P.K. Ko, C. Hu, “Hot-Electron Induced Traps Studied Through the Random Telegraph Noise,” IEEE Electron Device Letters, Vol. 12, No. 6, June 1991, pp. 273-275.
  278. J. Tao, K.K. Young, C.A. Pico, N.W. Cheung, C. Hu, “Electromigration Characteristics of Al/W Via Contact Under Unidirectional and Bidirectional Current Conditions,” Proc. 8th International IEEE VLSI Multilevel Interconnection Conf. (VMIC), June 1991, pp. 390-392.
  279. S. Chiang, R. Wang, T. Speers, J. McCollum, E. Hamdy, C. Hu, “Experimental Evidence for the Morphology of the Antifuse,” Electronic Engineering , June, 1991, pp. 4548.
  280. H. Shin, C-C. King, T. Horiuchi, C. Hu, “Thin Oxide Charging Current During Plasma Etching of Aluminum,” IEEE Electron Device Letters, Vol. 12, No. 8, August 1991, pp. 404-406.
  281. J. Chen, R. Solomon, T.Y. Chan, P.K. Ko, C. Hu, “A CV Technique for Measuring Thin SOI Film Thickness,” IEEE Electron Device Letters, Vol. 12, No. 8, August 1991, pp. 453-455.
  282. Z.H. Liu, P. Nee, P.K. Ko, C. Hu, C. Sodini, B.J. Gross, T.P. Ma, Y.C. Cheng, “A Comparative Study of High-Field Endurance for Reoxidized-Nitrided Oxides and Fluorinated Oxides,” Extended Abstracts of the International Conf. on Solid State Devices and Materials, Yokohama, Japan, August 1991, pp. 26-28.
  283. Best Paper Award, H. Shin, C-C. King, C. Hu, “Characterization of Thin Oxide Damage During Plasma Etching and Ashing Processes,” American Vacuum Society Plasma Etch Symp., San Jose, Sept. 19, 1991, pp. 42-45.
  284. P.M. Lee, P.K. Ko, C. Hu, “A Simple Method to Predict Hot-Carrier Degradation in CMOS Inverter-Based Circuits,” Proc. of IEICE Semiconductor Materials and Devices Workshop, Vol. 91, No. 244, September 26-27, 1991, pp. 57-63.
  285. J. Chen, K. Quader, P. Ko, C. Hu, “Hot Electron Gate Current and Degradation in P-Channel SOI MOSFETs,” Proc. IEEE International SOI Conf., Vail, Colorado, October 1991, pp. 8-9.
  286. F. Assaderaghi, J. Chen, R. Solomon, T. Chan, P. Ko, C. Hu, “Time Dependence of Fully Depleted SOI MOSFET’s Subthreshold Current,” Proc. IEEE International SOI Conf., Vail, Colorado, October 1991, pp. 32-33.
  287. J. Chen, A. Lee, P. Fang, P. Ko, C. Hu, R. Solomon, T. Chan, “Interface Quality of SOI MOSFET’s Reflected in Noise and Mobility,” Proc. IEEE International SOI Conf., Vail, Colorado, October 1991, pp. 100-101.
  288. F. Assaderaghi, J. Chen, R. Solomon, T.Y. Chan, P.K. Ko, C. Hu, “Transient Behavior of Subthreshold Characteristics of Fully Depleted SOI MOSFET’s,” IEEE Electron Device Letters, Vol. 12, No. 10, October 1991, pp. 518-520.
  289. Keynote Address, C. Hu, “A Migration Path of Future Silicon MOSFET,” 10th Symp. on Future Electron Devices (MITI, Japan), Tokyo, Japan, October 1991, pp. 185-191.
  290. H.P. Zappe, C. Hu, “A p-v-n Diode Model for CMOS Latchup,” Solid-State Electronics, Vol. 34, No. 11, pp. 1275-1279, November 1991, pp. 1275-1279.
  291. E. Rosenbaum, R. Rofan, C. Hu, “Effect of Hot-Carrier Injection on n- and p-MOSFET Gate Oxide Integrity,” IEEE Electron Device Letters, Vol. 12, No. 11, November 1991, pp. 599-601.
  292. R. Rofan, C. Hu, “Stress-Induced Oxide Leakage,” IEEE Electron Devices Letters, Vol. 12, No. 11, November 1991, pp. 632-634.
  293. C. Hu, “MOS Devices,” Semiconductor Technology University White Papers, Semiconductor Research Corporation, November 1991, pp. 167-190.
  294. C.J. Hegarty, J.C. Lee, C. Hu, “Enhanced Conductivity and Breakdown of Oxides Grown on Heavily Implanted Substrates,” Solid State Electronics , Vol. 34, No. 11, Nov. 1991, pp. 1207-1213.
  295. Z.H. Liu, J.H. Huang, J. Duster, P.K. Ko, C. Hu, M.C. Jeng, Y.C. Cheng, “Threshold Voltage Modeling for Deep-Submicrometer Conventional LDD MOSFETs at 300K and 85K,” Proc. International Semiconductor Device Research Symp., Charlottesville, Virginia, December 4-6, 1991, pp. 411-414.
  296. J. Tao, K.K. Young, C.A. Pico. N.W. Cheung, C. Hu, “Electromigration Characteristics of Tungsten Plug Vias Under Pulse and Bidirectional Current Stressing,” IEEE Electron Device Letters, Vol. 12, No. 12, December 1991, pp. 646-648.
  297. K.N. Quader, C. Li, R. Tu, E. Rosenbaum, P. Ko, C. Hu, “A New Approach for Simulation of Circuit Degradation Due to Hot-Electron Damage in NMOSFETs,” Tech. Digest IEEE International Electron Devices Meeting, Washington, D.C., December 1991, pp. 337-340.
  298. J. Chen, F. Assaderaghi, H. Wann, P. Ko, C. Hu, “An Accurate Model of Thin Film SOI MOSFET Breakdown Voltage,” Tech. Digest IEEE International Electron Devices Meeting, Washington, D.C., December 1991, pp. 671-674.
  299. Best Student Paper, E. Rosenbaum, Z. Liu, C. Hu, “The Effects of Oxide Stress Waveform on MOSFET Performance,” Tech. Digest IEEE International Electron Devices Meeting, Washington, D.C., December 1991, pp. 719-722.
  300. Z.H. Liu, E. Rosenbaum, P. Ko, C. Hu, Y.C. Cheng, C.G. Sodini, B.J. Gross, T.P. Ma, “A Comparative Study of the Effects of Dynamic Stressing on High-Field Endurance and Stability of Reoxidized-Nitrided, Fluorinated and Conventional Oxides,” IEEE International Electron Devices Meeting, Technical Digest, Washington, D.C., December 1991, pp. 723-726.
  301. E.M.A. Ravanelli, C. Hu, “Device-Circuit Mixed Simulation of VDMOS Charge Transients,” Solid State Electronics, Vol. 34, No. 12, December 1991, pp. 1353-1360.
  302. Z.H. Liu, P. Nee, P.K. Ko, C. Hu, C.G. Sodini, B.J. Gross, T-P. Ma, Y.C. Cheng, “Field and Temperature Acceleration of Time-Dependent Dielectric Breakdown for Reoxidized-Nitrided and Florinated Oxides,” IEEE Electron Device Letters, Vol. 13, No. 1, January 1992, pp. 41-43.
  303. C. Hu, “IC Reliability Simulation,” IEEE Journal Solid State Circuits, Vol. 27, No. 3, March 1992, pp. 241-246.
  304. J. Tao, K.K. Young, N.W. Cheung, C. Hu, “Comparison of Electromigration Reliability of Tungsten and Aluminum Vias Under DC and Time-Varying Current Stressing,” Proc. IEEE International Reliability Physics Symp., March 1992, pp. 338-343.
  305. C. Jiang, C. Hu, C.H. Chen, P.N. Tseng, “Impact of Inter-Metal-Oxide Deposition Condition on NMOS and PMOS Transistor Hot Carrier Effect,” Proc. IEEE International Reliability Physics Symp., March 1992, pp. 122-126.
  306. K. Quader, P. Fang, P.K. Ko, C. Hu, “Simulation of Hot-Carrier-Induced CMOS Circuit Degradation,” Proc. IEEE International Reliability Physics Symp., March 1992, pp. 16-23.
  307. V. Jain, D. Pramanik, S.R. Nariani, C. Hu, “Internal Passivation for Suppression of Device Instabilities Induced by Backend Processes,” Proc. IEEE International Reliability Physics Symp., March 1992, pp. 11-15.
  308. H. Shin, C.C. King, C. Hu, “Thin Oxide Damage by Plasma Etching and Ashing Process,” Proc. IEEE International Reliability Physics Symp., March 1992, 37-41.
  309. Tutorial, R. Moazammi, C. Hu, “Modeling and Characterizing SiO 2 Reliability,” Tutorial Notes, International Reliability Physics Symp. , March 1992, p. 5.1.
  310. Invited Paper, C. Hu, “Simulating Hot-Carrier Effects on Circuit Performance,” Semiconductor Science and Technology, Adam Hilger Publisher Vol. 7, pp. B555-B558, March 1992.
  311. C. Hu, “The Berkeley Reliability Simulator BERT: An IC Reliability Simulator,” Microelectronics Journal, Vol. 233, No. 2. April, 1992, pp. 97-102.
  312. K.N. Quader, P.K. Ko, C. Hu, P. Fang, J.T. Yue, “Simulations of CMOS Circuit Degradation Due to Hot-Carrier Effects,” Reliability Physics Symposium, 30th Annual Proceedings, pp. 16-23, April 1992.
  313. J. Chen, R. Solomon, T.Y. Chan, P.K. Ko, C. Hu, “Parasitic Capacitances of SOI MOSFET’s,” Proc. of the Fifth International Symp. on Silicon-on-Insulator Technology and Devices, Electrochemical Society Proc. Vol. 92-13, May 1992, pp. 89-90.
  314. S.R. Nariani, K.Y. Chang, M. Biegel, C. Hu, “An ASIC-Compatible EEPROM Technology,” Proc. of the IEEE Custom Integrated Circuits Conf., Boston, MA., May 1992, pp. 9.5.1- 9.5.4.
  315. Y. Fong, G.C. Liang, T. Van Duzer, C. Hu, “Channel Width Effect on MOSFET Breakdown,” IEEE Transactions on Electron Devices, Vol.39, No.5, pp. 1265-1267, May, 1992.
  316. K. Schuegraf, C. King, C. Hu, “Ultra-Thin Silicon Dioxide Leakage Current and Scaling Limit,” Proc. Symp. on VLSI Technology Digest , June 1992, pp. 18-19.
  317. S. Chiang, R. Wang, T. Speers, J. McCollum, E. Hamdy, C. Hu, “Conductive Channel in ONO Formed by Controlled Dielectric Breakdown,” Proc. Symp. on VLSI Technology Digest , June 1992, pp. 20-21.
  318. C. Hu, “Built-in Reliability,” Nikkei Microdevices (Japanese), June 1992, pp. 91-97.
  319. S.A. Parke, E. Moon, H-J. Wenn, P.K. Ko, C. Hu, “Design for Suppression of Gate-Induced Drain Leakage in LDD MOSFET’s Using a Qusasi-Two Dimensional Analytical Model,” IEEE Trans. Electron Devices, Vol. 39, No. 7, July 1992, pp. 1694-1703.
  320. Z. Liu, H.J. Wann, P.K. Ko, C. Hu, Y.C. Cheung, “Effects of N2O Anneal and Reoxidation on Thermal Oxide Characteristics,” IEEE Electron Device Letters, Vol. 13, No. 8, Aug. 1992, pp. 402-404.
  321. J. Tao, N.W. Cheung, C. Hu, H.K. Kang, S.S. Wong, “Electromigration Performance of Electroless Plated Copper/Pd-Silicide Metallization,” IEEE Electron Device Letters, Vol. 13, No. 8, Aug. 1992, pp. 433-435.
  322. R. Moazzami, C. Hu, W.H. Shepherd, “Electrical Characteristics of Ferroelectric PZT Thin Films for DRAM Applications,” IEEE Trans. Electron Devices, Vol. 39, No. 9, Sept. 1992, pp. 2044-2049.
  323. Keynote Address, C. Hu, “Future Evolution of MOSFETs,” American Vacuum Society Plasma Etch 1992 Symp., Santa Clara, CA., Sept. 17, 1992, pp. 1-4.
  324. K. Noguchi, H. Shin, C. Hu, “Gate Oxide Damage by Plasma Oxide Deposition and Via Etch,” American Vacuum Society Plasma Etch 1992 Symp., Santa Clara, CA., Sept. 17, 1992, pp. 18-19.
  325. Y. Wei, Y. Loh, C. Wang, C. Hu, “MOSFET Drain Engineering for ESD Performance,” Proc. Electrical Overstress/Electrostatic Discharge Symp., Dallas, TX., Sept. 16-18, 1992, pp. 143-148.
  326. Invited Paper, C. Hu, N.W. Cheung, J. Tao, B.K. Liew, “Modeling Electromigration Lifetime Under Pulsed and AC Current Stress,” Proc. SPIE , San Jose, CA., Vol. 1805, Submicrometer Metallization, Sept. 1992, pp. 244-250.
  327. J. Chen, R. Solomon, T.Y. Chan, P.K. Ko, C. Hu, “Threshold Voltage and C-V Characteristics of SOI MOSFET’s Related to Si Film Thickness Variation on SIMOX Wafers,” IEEE Trans. on Electron Devices, Vol. 39, No. 19, Oct. 1992, pp. 2346-2353.
  328. J. Chen, F. Assaderaghi, P.K. Ko, C. Hu, “The Enhancement of Gate-Induced-Drain-Leakage (GIDL) Current in SOI MOSFET and Its Impact on SOI Device Scaling,” Proc. IEEE International SOI Conf., Fort Lauderdale, FL., Oct. 6-8, 1992, pp. 84-85.
  329. F. Assaderaghi, J. Chen, P. Ko, C. Hu, “Measurement of Electron and Hole Saturation Velocities in Silicon Inversion Layers Using SOI MOSFETs,” Proc. IEEE International SOI Conf., Fort Lauderdale, FL., Oct. 6-8, 1992, pp. 112-113.
  330. S.A. Parke, C. Hu, P.K. Ko, “Complimentary High Performance Lateral BJT’s in a SIMOX C-BiCMOS Technology,” Proc. IEEE International SOI Conf., Fort Lauderdale, FL., Oct. 6-8, 1992, pp. 142-143.
  331. H.J. Park, P.K. Ko, C. Hu, “A Non-Quasistatic MOSFET Model for SPICE-AC Analysis,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 11, No. 10, October 1992. pp. 1247-1257.
  332. E. Nowak, E. Johnson, M. Hong, Y. Han, C. Wang, Y.T. Loh, C. Hu, “Optimization of Punchthrough Effects for Deep Submicron N-Channel MOSFETs,” Proc. 3rd International Conf. Solid State and Integrated Circuit Technology, Beijing, CHINA, Oct. 1992, pp. 76-79.
  333. Y. Wei, L. Ding, C. Wang, C. Hu, “Performance of 3V CMOS Circuit,” Proc. 3rd International Conf. Solid State and Integrated Circuit Technology , Beijing, CHINA, Oct. 1992, pp. 324-326.
  334. H. Shin, C. Hu, “Plasma-Etching Induced Damage in Thin Oxide,” Proc. IEEE/SEMI Adv. Semiconductor Manufacturing Conf. , Minneapolis, MN., Oct. 1992, pp. 79-83.
  335. Z. Liu, H-J. Wann, P.K. Ko, Y.C. Cheng, C. Hu, “Improvement of Charge Trapping Characteristics of N2O-Annealed Thin Oxides,” IEEE Electron Device Letters , Vol. 13, No. 10, October 1992, pp. 519-521.
  336. Plenary Session Address, C. Hu, “Silicon MOSFETs in the Next Twenty Years,” Proc. International. Electron Devices and Materials Symp. , Taipei, Taiwan, November 1992, pp. 4-6.
  337. B-K. Liew, P. Fang, N.W. Cheung, C. Hu, “Circuit Reliability Simulator for Interconnect, Via, And Contact Electromigration,” IEEE Trans. on Electron Devices, Vol. 39, No. 11, November 1992, pp. 2472-2479.
  338. J. Chen, F. Assaderaghi, P.K. Ko, C. Hu, “The Enhancement of Gate-Induced-Drain-Leakage (GIDL) Current in Short-Channel SOI MOSFET and It’s Application in Measuring Lateral Bipolar Current Gain,” IEEE Trans. Device Letter, Vol. 13, No. 11, November 1992, pp. 572-574.
  339. H. Shin, C. Hu, “Dependence of Plasma-Induced Oxide Charging Current on Al Antenna Geometry,” IEEE Electron Device Letters, Vol. 13, No. 12, Dec. 1992, pp. 600-602.
  340. J. Chen, S. Parke, J. King, F. Assaderaghi, P.K. Ko, C. Hu, “High Speed SOI Technology with 12ps/18ps Gate Delay Operating at 5V/1.5V,” Tech. Digest International Electron Devices Meeting, San Francisco, CA., Dec. 1992, pp. 35-38.
  341. R. Moazzami, C. Hu, “Stress-Induced Current in Thin Silicon Dioxide Films,” Tech. Digest International Electron Devices Meeting, San Francisco, CA., Dec. 1992, pp. 139-142.
  342. H-J. Wann, P.K. Ko, C. Hu, “Gate-Induced Band-to-Band Tunneling Leakage Current in LDD MOSFET’s,” Tech. Digest International Electron Devices Meeting, San Francisco, CA., Dec. 1992, pp. 147-150.
  343. S. Parke, F. Assaderaghi, J. Chen, J. King, P.K. Ko, C. Hu, “A Versatile SOI BiCMOS Technology with Complementary Lateral BJT’s,” Tech. Digest International Electron Devices Meeting, San Francisco, CA., Dec. 1992, pp. 453-456.
  344. E.R. Minami, K.N. Quader, P.K. Ko, C. Hu, “Prediction of Hot-Carrier Degradation in Digital CMOS VLSI by Timing Simulator,” Tech. Digest International Electron Devices Meeting, San Francisco, CA., Dec. 1992, pp. 539-542.
  345. C.C. Li, K.N. Quader, E.R. Minami, C. Hu, P.K. Ko, “A New Bi-Directional PMOSFET Hot-Carrier Degradation Model for Circuit Reliability Simulation,” Tech. Digest International Electron Devices Meeting, San Francisco, CA., Dec. 1992, pp. 547-550.
  346. J.H. Huang, Z.H. Liu, M.C. Jeng, P.K. Ko, C. Hu, “A Physical Model for MOSFET Output Resistance,” Tech. Digest International Electron Devices Meeting, San Francisco, CA., Dec. 1992, pp. 569-572.
  347. Invited Paper, C. Hu, “Interconnect Devices for Field Programmable Gate Array,” Tech. Digest International Electron Devices Meeting, San Francisco, CA., Dec. 1992, pp. 591-594.
  348. S. Chiang, R. Farouhi, W. Chen, F. Hawley, J. McCollum, E. Hamdy, C. Hu, “Antifuse Structure Comparison for Field Programmable Gate Arrays,” Tech. Digest International Electron Devices Meeting, San Francisco, CA., Dec. 1992, pp. 611-614.
  349. Z.H. Liu, J.T. Krick, H.J. Wann, P.K. Ko, C. Hu, Y.C. Cheng, “The Effects of Furnace N2O Annealing on MOSFETs,” Tech. Digest International Electron Devices Meeting, San Francisco, CA., Dec. 1992, pp. 625-628.
  350. M.H. Kiang, J. Tao, W. Namjoong, C. Hu, M. Lieberman and N.W. Cheung, H-K Kang, S. Wong, “Planarized Copper Interconnects by Selective Electroless Plating,” Proc. Materials Research Society Symp. , Boston, MA., Vol. 265, Materials Reliability in Microelectronics II, pp. 187-197, 1992.
  351. Z.H. Liu, C. Hu, J-H. Huang, T-Y. Chan, M-C. Jeng, P.K. Ko, Y.C. Cheng, “Threshold Voltage Model for Deep-Submicrometer MOSFET’s,” IEEE Trans. on Electron Devices, Vol. 40, No. 1, January 1993, pp. 86-95.
  352. S.A. Parke, C. Hu, P. Ko, “A High Performance Lateral Bipolar Transistor Fabricated on SIMOX,” IEEE Electron Device Letters, Vol. 14, No. 1, January 1993, pp. 33-35.
  353. C. Hu, “Circuit Reliability Simulation,” Proc. IEEE Symp. on VLSI Technology CAD, January 1993, Santa Clara, CA., pp. 430-500.
  354. P.K. Ko, J.H. Huang, Z.H. Liu, C. Hu, “BSIM3 for Analog and Digital Circuit Simulation,” IEEE Symp. on VLSI Technology CAD , January 1993, pp. 400-429.
  355. R. Moazammi, C. Hu, “A High-Quality Stacked Thermal/ LPCVD Gate Oxide Technology for ULSI,” IEEE Electron Device Letters, Vol. 14, No. 2, February 1993, pp. 72-73.
  356. H. Shin, K. Noguchi, X.Y. Qian, N. Jhan, G. Hills, C. Hu, “Spatial Distribution of Thin Oxide Charging in Reactive Ion Etcher and MERIE Etcher,” IEEE Electron Device Letters, Vol. 14, No. 2, February 1993, pp. 88-90.
  357. K.F. Schuegraf, C. Hu, “Hole Injection Oxide Breakdown Model for Very Low Voltage Lifetime Extrapolation,” Proc. IEEE International Reliability Physics Symp., Atlanta, GA., March 1993, pp. 7-12.
  358. C. Jiang, E. Johnson, J.J. Shaw, C. Hu, “AC Hot-Carrier Degradation in a Voltage Controlled Oscillator,” Proc. IEEE International Reliability Physics Symp., Atlanta, GA., March 1993, pp. 53-56.
  359. H. Shin, K. Noguchi, C. Hu, “Thickness and Other Effects on Oxide and Interface Damage by Plasma Processing,” Proc. IEEE International Reliability Physics Symp., Atlanta, GA., March 1993, pp. 272-279.
  360. Tutorial, C. Hu, “Simulating Hot Electron Effects on Circuit Performance,” Tutorial Notes, IEEE International Reliability Physics Symp., March 1993, pp. 1C1-1C34.
  361. C. Hu, H. Shin, “Characterization and Modeling of Thin Oxide Damage by Plasma Etch,” Sematech Plasma Damage Symp., Austin, Texas, April 1993, pp. W 3.1-27.
  362. J.C. Chen, Z. Liu, J.T. Krick, P.K. Ko, C. Hu, “Degradation of N2O Annealed MOSFET Characteristics in Response to Dynamic Oxide Stressing,” IEEE Electron Device Letters, Vol. 14, No. 15, May 1993, pp. 225-227.
  363. S.A. Parke, C. Hu, P.K. Ko, “Bipolar -FET Hybride-Mode Operation of Quarter-Micrometer SOI MOSFET’s,” IEEE Electron Device Letters, Vol. 14, No. 15, May 1993, pp. 234-236.
  364. J. Tao, N.W. Cheung, C. Hu, “Electromigration Characteristics of Copper Interconnects,” IEEE Electron Device Letters, Vol. 14, No. 15, May 1993, pp. 249-251.
  365. J.H. Huang, G.B. Zhang, Z.H. Liu, J. Duster, S.J. Wann, P. Ko, C. Hu, “Temperature Dependence of MOSFET Substrate Current,” IEEE Electron Device Letters, Vol. 14, No. 15, May 1993, pp. 268-271.
  366. Y. Wei, Y. Loh, C. Wang, C. Hu, “I/O Device Drain Engineering for a 5V 0.6mm CMOS Technology,” Proc. of Tech. Papers , IEEE International Symp. on VLSI Technology, Systems and Applications, Taipei, Taiwan, May 12-14, 1993, pp. 6-10.
  367. K.F. Schuegraf, C.C. King, C. Hu, “Impact of Polysilicon Depletion in Thin Oxide CMOS Technology,” Proc. of Tech. Papers , IEEE International Symp. on VLSI Technology, Systems and Applications, Taipei, Taiwan, May 12-14, 1993, pp. 86-90.
  368. H-J. Wann, P.K. Ko, C. Hu, “A Channel Field Model of SOI MOSFET,” Proc. of Tech. Papers , IEEE International Symp. on VLSI Technology, Systems and Applications, Taipei, Taiwan, May 12-14, 1993, pp. 133-37.
  369. K.N. Quader, W.Y. Chan, P.K. Ko, C. Hu, “Hot-Carrier Reliability of Mixed Mode Analog/Digital Technologies,” Proc. of Tech. Papers , IEEE International Symp. on VLSI Technology, Systems and Applications, Taipei, Taiwan, May 12-14, 1993, pp. 168-172.
  370. S. Parke, F. Assaderaghi, C. Hu, P.K. Ko, “Nearly-Fully-Depleted (NFD) 0.15 mm SOI CMOS in a CBiCMOS Technology,” Proc. of Tech. Papers , IEEE International Symp. on VLSI Technology, Systems and Applications, Taipei, Taiwan, May 12-14, 1993, pp. 227-231.
  371. F. Assaderaghi, K. Hui, S. Parke, J. Duster, P.K. Ko, C. Hu, “Study of Current Drive in Deep Sub-Micrometer SOI PMOSFET’s,” Proc. of Tech. Papers , IEEE International Symp. on VLSI Technology, Systems and Applications, Taipei, Taiwan, May 12-14, 1993, pp. 232-236.
  372. J.H. Huang, Z. H. Liu, M.C. Jeng, P. K. Ko, C. Hu, “A Robust Physical and Predictive Model for Deep-Submicrometer MOS Circuit Simulation,” Proc. IEEE Custom Integrated Circuit Conf., San Diego, CA., May 1993, pp. 14.2.1-14.2.4.
  373. K.N. Quader, E.R. Minami, W.J. Huang, P.K. Ko, C. Hu, “Hot-Carrier Reliability Design Guidelines for CMOS Logic Circuits,” Proc. IEEE Custom Integrated Circuit Conf., San Diego, CA., May 1993, pp. 30.7.1-30.7.4.
  374. Tutorial, C. Hu, “Design for Reliability,” Educational Session Notes, IEEE Custom Integrated Circuit Conf., San Diego, CA., May 1993, p. 2.1.
  375. K.N. Quader, P.K. Ko, C. Hu, “A New Insight into Correlation between DC and AC Hot Carrier Degradation of MOS Devices,” IEEE Symp. on VLSI Technology, Kyoto, JAPAN, May 1993, pp. 13-14.
  376. K. Schuegraf, C. Hu, “Oxide Breakdown Model for Very Low Voltages,” IEEE Symp. on VLSI Technology, Kyoto, JAPAN, May 1993, pp. 43-44.
  377. H.J. Wann, S. A. Parke, P.K. Ko, C. Hu, “Suppressing Flash EEPROM Erase Leakage with Negative Gate Bias and LDD Erase Junction,” IEEE Symp. on VLSI Technology, Kyoto, JAPAN, May 1993, pp. 81-82.
  378. Invited Paper, C. Hu, “Towards ULSI Reliability by Design,” Proc. of the 4th International Symp. on Ultra Large Scale Integration Science and Technology: Electrochemical Society (ECS), May 1993, Vol. 93-23, pp. 158-162.
  379. H. Shin, C. Hu, “Monitoring Plasma-Induced Damage to Thin Oxide,” IEEE Trans. on Semiconductor Manufacturing, Vol. 6, No. 2, May 1993, pp. 96-102.
  380. Invited Paper, C. Hu, “Future CMOS Scaling and Reliability,” Proc. of the IEEE, Vol. 81, No. 5, May 1993, pp. 682-689.
  381. V. Jain, D. Pramenik, C. Hu, “Novel Technique for Estimating Charge and Thickness Variations in Dielectrics Used for Planarization,” Proc. of VLSI Multi-Level Interconnect, San Jose, CA, June 1993, pp. 535-538.
  382. F. Assaderaghi, S. Parke, J. King, J. Chen, P.K. Ko, C. Hu, “High-Performance Sub-Quarter-Micrometer PMOSFET’s on SOI,” IEEE Electron Device Letters, Vol. 14, No. 6, June 1993, pp. 298-300.
  383. J. Tao, K.K. Young, N.W. Cheung, C. Hu, “Electromigration Reliability of Tungsten and Aluminum Vias and Improvements under AC Current Stress,” IEEE Trans. on Electron Devices, Vol. 40 No. 8, August 1993, pp. 1398-1405.
  384. H. Shin, N. Jha, X-Y. Qian, G.W. Hills, C. Hu, “Plasma Etching Charge-Up Damage to Thin Oxides,” Solid State Technology, August 1993, pp. 29-36.
  385. Invited Paper, C. Hu, “Silicon-on-Insulator for High Speed ULSI,” Extended Abstracts of the International Conf. on Solid State Devices and Materials, Chiba, Japan, August 1993, pp. 137-139.
  386. E.D. Nowak, C. Hu, “A Simple Method for Analyzing Bulk Versus Surface Punchthrough Current,” Extended Abstracts of the International Conf. on Solid State Devices and Materials, Chiba, Japan, August 1993, pp. 488-490.
  387. J.S. Duster, Z.H. Liu, P.K. Ko, C. Hu, “Temperature Effects of the Inversion Layer Electron and Hole Mobility of MOSFETs from 85K to 500K,” Extended Abstracts of the International Conf. on Solid State Devices and Materials, Chiba, Japan, August 1993, pp. 835-837.
  388. G.W. Hills, N. Jha, X.Y. Qian, H. Shin, K. Noguchi, and C. Hu, “Charging Studies in a Magnetically Enhanced Plasmas,” Proc. 11th International Symposium on Plasma Chemistry, August 1993.
  389. H. Shin, C. Hu, “Plasma Etching Antenna Effect on Oxide-Silicon Interface Reliability,” Solid State Electronics, Vol. 36, No. 9, September 1993, pp. 835-837.
  390. Y. Wei, Y. Loh, C. Wang, C. Hu, “Effect of Substrate Contact on ESD Failure of Advanced CMOS Integrated Circuits,” 15th Annual Electrical Overstress/Electrostatic Discharge Symp., Lake Buena Vista, FL, September 1993, pp. 221 – 224.
  391. C. Hu, “Building-in Reliability,” New ASIC Design Techniques 94 (Japanese), Nikkei Business Publications, Inc., Tokyo, Japan, 1993, pp. 145-148.
  392. F. Assaderaghi, C. Hu, P.K. Ko, J. Duster, D. Sinitsky, J. Bokor, “Direct Observation of Velocity Overshoot in Silicon Inversion Layers,” TECHCON Extended Abstracts, September 1993, pp. 265-267.
  393. E.R. Minami, K.N. Quader, C. Hu, C. Li, E. Rosenbaum, P.K. Ko, “New Approaches to Digital MOS Circuit Reliability Simulation,” TECHCON Extended Abstracts, September 1993, pp. 268-270.
  394. J.H. Huang, P.K. Ko, Z.H. Liu, C. Hu, M.C. Jeng, “A Robust Physical and Predictive Model for Deep-Submicrometer MOS Circuit Simulation,” TECHCON Extended Abstracts, September 1993, pp. 355-357.
  395. C.K. Szeto, P.K. Ko, C. Hu, “Non-Quasistatic Modeling of the BJT Quasi-neutral base,” IEEE Bipolar Circuits and Tech. Meeting, Sept. 1993, pp. 197-200.
  396. N. Jha, H. Shin, G.W. Hills, X.Y. Qian, and C. Hu, “Factors Affecting Charge-up in a Magnetically Enhanced RIE Polysilicon Etcher,” Proc. Electrochemical Society, Vol. 93-12, September 1993.
  397. F. Assaderaghi, P.K. Ko, C. Hu, “Observation of Velocity Overshoot in Silicon Inversion Layer,” IEEE Electron Device Letters, Vol. 14, No. 10, October 1993, pp. 484-486.
  398. H. Wann, J. King, J. Chen, P.K. Ko, C. Hu, “Hot-Carrier Currents of SOI MOSFETs,” Proc. IEEE International SOI Conf. , October 1993, pp. 118-119.
  399. F. Assaderaghi, P.K. Ko, C. Hu, “Room Temperature Observation of Velocity Overshoot in Silicon Inversion Layers,” Proc. IEEE International SOI Conf., October 1993, pp. 116-117.
  400. M. Chan, F. Assaderaghi, S.A. Parke, S.S. Yuen, P.K. Ko, C. Hu, “Recess Channel Structure for Reducing Source/Drain Series Resistance in Ultra Thin SOI MOSFETs,” 1993 IEEE International SOI Conference Proceedings, October 1993, pp. 172-173.
  401. R.H. Tu, E. Rosenbaum, W.Y. Chan, C.C. Li, E. Minami, K. Quader, P.K. Ko, C. Hu, “Berkeley Reliability Tools — BERT,” IEEE Trans. on CAD, Vol. 12, No. 10, October 1993, pp. 1524-1534.
  402. E.Y. Chao, C. Hu, S. Wu, G.P. Li, P. Liu, J. White, R. Kjar, “Annealing Characteristics of Radiation Induced Leakage in SOS MOSFETs,” SOI Conference, 1993, Proceedings, pp. 84-85, October, 1993.
  403. H. Shin, K. Noguchi, C. Hu, “Modeling Oxide Thickness Dependence of Charging Damage by Plasma Processing,” IEEE Electron Device Letters., Vol. 14, No. 11, November 1993, pp. 509-511.
  404. H. Shin, Z. Ma, C. Hu, “Impact of Plasma Charging Damage and Diode Protection on Scaled Thin Oxide,” Tech. Digest, International Electron Device Meeting, December 1993, pp. 467-470.
  405. K. Quader, P. Ko, C. Hu, “Projecting CMOS Circuit Hot-Carrier Reliability from DC Device Lifetime,” Tech. Digest, International Electron Device Meeting, December 1993, pp. 511-514.
  406. H. Wann, C. Hu, “A Capacitorless DRAM,” Tech. Digest, International Electron Device Meeting, December 1993, pp. 635-638.
  407. W.M. Huang, R. Racanelli, B.Y. Hwang, Z.J. Ma, P.K. Ko, C. Hu, “ULSI-Quality Gate Oxide on Thin-Film-Silicon-on-Insulator,” Tech. Digest, International Electron Device Meeting, December 1993, pp. 735-738.
  408. J. Tao, N.W. Cheung, C. Hu, “Metal Electromigration Damage Healing Under Bidirectional Current Stress,” IEEE Electron Device Letters, Vol. 14, No. 12, December 1993, pp. 554-556.
  409. K.N. Quader, C.C. Li, R. Tu, E. Rosenbaum, P.K. Ko, C. Hu, “A Bidirectional NMOSFET Current Reduction Model for Simulation of Hot-Carrier-Induced Current Degradation,” IEEE Trans. on Electron Device, Vol. 40, No. 12, December 1993, pp. 2245-2254.
  410. E. Rosenbaum, C. Hu, “Silicon Dioxide Breakdown Lifetime Enhancement Under Bipolar Bias Conditions,” IEEE Trans. on Electron Device, Vol. 40, No. 12, December 1993, pp. 2287-2295.
  411. K.F. Schuegraf, C. Hu, “Defect Breakdown Lifetime Projection of Thin SiO2 at Low Voltages,” Proc. International Semiconductor Device Research Symp., Dec. 1993, pp. 253-256.
  412. M. Chan, Z.J. Ma, F. Assaderaghi, C.T. Nguyen, P.K. Ko, C. Hu, “A Low-Barrier Body Contact Scheme for SOI MOSFETs to Eliminate the Floating Body Effect,” Proc. International Semiconductor Device Research Symp., Dec. 1993, pp. 341-344.
  413. E.D. Nowak, L. Ding, Y.T. Loh, M. Hong, C. Hu, “An Arsenic LDD for 3.3 Volt N-channel MOSFET Applications,” Proc. International Semiconductor Device Research Symp., Dec. 1993, pp. 365-368.
  414. J.C. King, J. Kuriowa, C. Hu, “Hot Carrier Burn-in for MOS Devices,” Proc. International Semiconductor Device Research Symp., Dec. 1993, pp. 369-372.
  415. M. Chan, F. Assaderaghi, S. Parke, C. Hu, P.K. Ko, “Recessed-channel Structure for Fabricating Ultrathin SOI MOSFET with Low Series Resistance,” IEEE Electron Device Letters , Vol. 15, No. 1, January 1994, pp. 22-24.
  416. Review Paper, C. Hu, “SOI (Silicon-On-Insulator) for High Speed Ultra Large Scale Integration,” Japan Journal of Applied Physics, Vol. 33, January 1994, pp. 365-369.
  417. C. Hu, “Low Voltage CMOS Device Scaling,” Digest of Technical Papers, International Solid-State Circuits Conference, February 1994, pp. 86-87.
  418. Invited Paper, C. Hu, “Hot Electron Effects – Closing the Gap Between Devices and Circuits,” International Conference on Advanced Microelectronic Devices and Processing, Sendai, Japan, March 1994, pp. 303-306.
  419. Z.J. Ma, J.C. Chen, Z.H. Liu, J.T. Krick, Y.C. Cheng, C. Hu, P.K. Ko, “Suppression of Boron Penetration in P+ Polysilicon Gate PMOSFETs Using Low Temperature Gate Oxide N2O Anneal,” IEEE Electron Device Letters, Vol. 15, No. 3, March 1994, pp. 109-111.
  420. K.N. Quader, E.R. Minami, W-J. Huang, P.K. Ko, C. Hu, “Hot-Carrier Reliability Design Guidelines for CMOS Logic Circuits,” IEEE Journal of Solid State Circuits, Vol. 29, No. 3, March 1994, pp. 253-260.
  421. Tutorial, C. Hu, “Integrated Circuit Damage Due to Electrical Stress,” 1994 International Reliability Physics Symposium Tutorial Notes, April 1994, pp. 7b.1-7b.14.
  422. Z.J. Ma, H.J. Wann, M. Chan, J. King, Y.C. Cheng, P.K. Ko, C. Hu, “Characterization of Hot-Carrier Effects in Thin-Film Fully Depleted SOI MOSFETs,” 1994 IEEE International Reliability Physics Symposium Proceedings, April 1994, pp. 52-56.
  423. K.F. Schuegraf, C. Hu, “Effects of Temperature and Defects on Breakdown Lifetime of Thin SiO2 at Low Voltage,” 1994 IEEE International Reliability Physics Symposium Proceedings, April 1994, pp. 126-135.
  424. M. Chan, S.S. Yuen, Z.J. Ma, K.Y. Hui, P.K. Ko, C. Hu, “Comparison of ESD Protection Capability of SOI and Bulk CMOS Output Buffers,” 1994 IEEE International Reliability Physics Symposium Proceedings, April 1994, pp. 292-298.
  425. R. Tu, G. Lum, P. Pavan, P. Ko, C. Hu, “Simulating Total-Dose Radiation Effects on Circuit Behavior,” 1994 IEEE International Reliability Physics Symposium Proceedings, April 1994, pp. 344-350.
  426. J. Tao, N.W. Cheung, C. Hu, “An Electromigration Failure Mode for Interconnects Under Pulsed and Bidirectional Current Stressing,” IEEE Transactions on Electron Devices, Vol. 41, No. 4, April 1994, pp. 539-545.
  427. Invited Paper, C. Hu, “Critical Issues of ULSI Gate Dielectrics,” SRC Topical Conference on ULSI Gate Dielectrics, Raleigh NC, May 11-12, 1994.
  428. Plenary Address, C. Hu, “ULSI Device Scaling and Reliability,” 38th International Symposium on Electron, Ion and Photon Beams, May 1994, p. PL1.
  429. G. Zhang, C. Hu, P. Yu, S. Chiang, E. Hamdy, “Characteristic Voltage of Programmed Metal-to-Metal Antifuses,” IEEE Electron Device Letters, Vol. 15, No. 5, May 1994, pp. 166-168.
  430. K.N. Quader, P. Fang, J.T. Yue, P.K. Ko, C. Hu, “Hot-Carrier Design Rules for Translating Device Degradation to CMOS Digital Circuit Degradation,” IEEE Transactions on Electron Devices,  Vol. 41, No. 5, May 1994, pp. 681-691.
  431. K.F. Schuegraf, C. Hu, “Hole Injection SiO2 Breakdown Model for Very Low Voltage Lifetime Extrapolation,” IEEE Transactions on Electron Devices  Vol. 41, No. 5, May 1994, pp. 761-767.
  432. P.M. Lee, T. Garfinkel, P.K. Ko, C. Hu, “Simulating the Competing Effects of P- and N- MOSFET Hot-Carrier Aging in CMOS Circuits,” IEEE Transactions on Electron Devices  Vol. 41, No. 5, May 1994, pp. 852-853.
  433. Invited Review, K.F. Schuegraf, C. Hu, “Reliability of Thin SiO2,” Semiconductor Science and Technology  Vol. 9, No. 5, May 1994, pp. 989-1004.
  434. Jiang Tao, N.W. Cheung, C. Hu, “Device Implementation of Copper Metallization for ULSI,” Proceedings 11th VLSI Multilevel Interconnection Conference (VMIC)  June 1994, pp. 465-471.
  435. Z.J. Ma, H.J. Wann, M. Chan, J.C. King, Y.C. Cheng, P.K. Ko, C. Hu, “Hot-Carrier Effects in Thin Film Fully-Depleted SOI MOSFETs,” IEEE Electron Device Letters, Vol. 15, No. 6, June 1994, pp. 218-220.
  436. Z.J. Ma, H. Shin, P.K. Ko, C. Hu, “Effect of Plasma Charging Damage on the Noise Performance of Thin Oxide MOSFETs,” IEEE Electron Device Letters  Vol. 15, No. 6, June 1994, pp. 224-226.
  437. C. Hu, “MOSFET Scaling in the Next Decade and Beyond,” Semiconductor International, June 1994, pp. 105-114.
  438. R. Tu, J. Huang, P. K. Ko, C. Hu, “MOSFET Saturation Voltage,” Solid State Electronics, Vol. 37, No. 7, July 1994, pp. 1445-1446.
  439. E.D. Nowak, L. Ding, Y.T. Loh, C. Hu, “Thin Bonded Wafer SOI CMOS Technology for Low Voltage High Performance Applications,” 1994 International Electron Devices and Materials Symposium , Hsinchu, Taiwan, July 1994, pp. 8-2-5 to 8-2-8.
  440. K. Schuegraf, C. Hu, “Effect of Temperature and Defects on Breakdown Lifetime of Thin SiO2 at Very Low Voltages,” IEEE Transactions on Electron Devices, Vol. 41, No. 7, July 1994, pp. 1227-1232.
  441. Z.J. Ma, Z. H. Liu, J.T. Krick, H.J. Huang, Y.C. Cheng, C. Hu, P.K. Ko, “Optimization of Gate Oxide N2O Anneal for CMOSFET’s at Room and Cryogenic Temperatures,” IEEE Transactions on Electron Devices, Vol. 41, No. 8, August 1994, pp. 1364-1372.
  442. G. Zhang, C. Hu, P. Yu, S. Chiang, E. Hamdy, “Metal-to-Metal Antifuses with Very Thin Silicon Dioxide Films,” IEEE Electron Device Letters, Vol. 15, No. 8, August 1994, pp. 310-312.
  443. S.R. Nariani, C.T. Gabriel, C. Hu, “Adding Mixed-Signal Capability to a Submicron Digital ASIC Process,” Solid State Technology , Vol. 37, no. 8, August 1994, pp. 79-83.
  444. K.F. Schuegraf, C. Hu, “Metal-Oxide-Semiconductor Field-Effect-Transistor Substrate Current during Fowler-Nordheim Tunneling Stress and Silicon-Dioxide Reliability,” Journal of Applied Physics, Vol. 76, no. 6, September 15, 1994, pp. 3695-3700.
  445. R. Tu, C. Wann, J. King, P.K. Ko, C. Hu, “SOI MOSFET Modeling Using an AC Conductance Technique to Determine Heating,” 1994 IEEE International SOI Conference Proceedings , Nantucket, MA, October 1994, pp. 21-22.
  446. E.D. Nowak, L. Ding, Y.T. Loh, C. Hu, “Speed Power and Yield Comparison of Thin Bonded SOI versus Bulk CMOS Technologies,” 1994 IEEE International SOI Conference Proceedings , Nantucket, MA, October 1994, pp. 41-42.
  447. M. Chan, J.C. King, P.K. Ko, C. Hu, “High Performance Bulk MOSFET Fabricated on SOI Substrate for ESD Protection and Circuit Applications,” 1994 IEEE International SOI Conference Proceedings , Nantucket, MA, October 1994, pp. 61-61.
  448. B. Yu, H.J. Wann, F. Assaderaghi, M. Chen, P.K. Ko, C. Hu, “Interface Characterization of Fully-Depleted SOI MOSFET by a Subthreshold I-V Method,” 1994 IEEE International SOI Conference Proceedings , Nantucket, MA, October 1994, pp. 63-64.
  449. K. Hui, M. Chan, F. Assaderaghi, C. Hu, P.K. Ko, “Body Self Bias in Fully Depleted and Non-fully Depleted SOI Devices,” 1994 IEEE International SOI Conference Proceedings , Nantucket, MA, October 1994, pp. 65-66.
  450. F. Assaderaghi, S. Parke, P.K. Ko, C. Hu, “A Novel Silicon-on-Insulator MOSFET for Ultra Low Voltage Operation,” 1994 IEEE Symposium on Low Power Electronics Digest of Technical Papers,” October, 1994, pp. 58-59.
  451. Z.J. Ma, Z.H. Liu, Y.C. Cheng, P.K. Ko, C. Hu, “New Insight into High-Field Mobility Enhancement of Nitrided-Oxide N-MOSFETs Based on Noise Measurements,” IEEE Transaction on Electron Devices , Vol. 41, No. 11, November 1994, pp. 2205-2209.
  452. J.C. King, C. Hu, “Effect of Low and High Temperature Anneal on Process-Induced Damage of Gate Oxide,” IEEE Electron Device Letters , Vol. 15, No. 11, November 1994, pp. 475-476.
  453. C. Hu, “Ultra-Large-Scale Integration Device Scaling and Reliability,” Journal of Vacuum Science and Technology B12 (6) Nov./Dec. 1994, pp. 3237-3241.
  454. Invited Paper, C. Hu, “An Engineering Model of VLSI Gate Oxide Breakdown,” 25th IEEE Semiconductor Interface Specialist Conference Abstracts , San Diego, December 1994, p. 1.
  455. M. Chan, K. Hui, R. Neff, C. Hu, P. Ko, “A Relaxation Time Approach to Model the Non-Quasistatic Transient Effect in MOSFETs,” International Electron Devices Meeting Technical Digest , San Francisco, December 1994, pp. 169-172.
  456. G. Zhang, C. Hu, P. Yu, S. Chiang, S. Eltoukhy, E. Handy, “Reliable Metal-to-Metal Oxide Antifuse,” International Electron Devices Meeting Technical Digest , San Francisco, December 1994, pp. 281-284.
  457. F. Assaderaghi, D. Sinitsky, H. Gaw, J. Bokor, P. Ko, C. Hu, “Saturation Velocity and Velocity Overshoot of Inversion Layer Electronics and Holes,” International Electron Devices Meeting Technical Digest , San Francisco, December 1994, pp. 479-482.
  458. J. King, W. Chan, C. Hu, “Efficient Gate Oxide Defect Screen for VLSI Reliability,” International Electron Devices Meeting Technical Digest , San Francisco, December 1994, pp. 597-600.
  459. K. Schuegraf, D. Park, C. Hu, “Reliability of Thin SiO 2 at Direct-Tunneling Voltages,” International Electron Devices Meeting Technical Digest , San Francisco, December 1994, pp. 609-612.
  460. F. Assaderaghi, D. Sinitsky, S. Parke, J. Bokor, P. Ko, C. Hu, “A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation,” International Electron Devices Meeting Technical Digest , San Francisco, December 1994, pp. 809-812.
  461. F. Assaderaghi, S. Parke, D. Sinitsky, J. Bokor, P.K. Ko, C. Hu, “A Dynamic Threshold Voltage MOSFET (DTMOS) for Very Low Voltage Operations,” IEEE Electron Devices Letters, Vol. 15, no. 12, December 1994, pp. 510-512.
  462. P. Pavan, R. Tu, E.R. Minami, G. Lum, C. Hu, “A complete radiationreliability software simulator,” IEEE Transaction on Nuclear Science, Vol. 41, no. 6, December 1994, pp. 2619-2630.
  463. M. Chan, J.C. King, P.K. Ko, C. Hu, “SOI/Bulk Hybrid Technology on SIMOX Wafers for High Performance Circuits with Good ESD Immunity,” IEEE Electron Device Letters, Vol. 16, No. 1, pp. 11-13 January 1995.
  464. R.H. Tu, C. Wann, J.C. King, P.K. Ko, C. Hu, “An AC Conductance Technique for Measuring Self-Heating in SOI MOSFET’s,” IEEE Electron Device Letters, Vol. 16, no. 2, February 1995, pp. 67-69.
  465. J. Tao, N. Cheung, C. Hu, “Modeling Electromigration Failures in TiN/Al-alloy/TiN Interconnects and TiN Thin Films,” International Reliability Physics Symposium Proceedings , April 1995, pp. 371-377.
  466. Invited Paper, C. Hu, “Circuit Reliability Simulation,” Materials Research Society Spring Meeting Abstracts, San Francisco, CA, April 1995, p. 17.
  467. T. Horiuchi, J.D. Burnett, C. Hu, “Bipolar Transistor Degradation Under Dynamic Hot Carrier Stress,” Solid State Electronics, Vol. 38, No. 4, April 1995, pp. 787-789.
  468. S.B. Kuusinen, C. Hu, “Hot-Carrier Induced Degradation of Critical Paths Modeled by Rule-Based Analysis,” Proceedings of 1995 IEEE Custom Integrated Circuits Conference, San Jose CA, May 1995, pp. 69-72.
  469. J.C. Chen, C. Hu, Z. Liu, P.K. Ko, “Realistic Worst-Case SPICE File Extraction Using BSIM3,” Proceedings of 1995 IEEE Custom Integrated Circuit Conference, San Jose, CA, May 1995, pp. 375-378.
  470. Invited Paper, C. Hu, N.W. Cheung, J. Tao, “Electromigration Under Bidirectional Current Stress,” Electrochemical Society Proceedings, Vol. 95-3, NV, May, 1995, p. 188-202.
  471. H.C. Wann, C. Hu, K. Noda, D. Sinitsky, F. Assaderaghi, J. Bokor, “Channel Doping Engineering of MOSFET with Adaptable Threshold Voltage Using Body Effect for Low Voltage and Low Power Application,” 1995 International Symposium on VLSI Technology, Systems, and Applications, Proceedings of Technical Papers, May 1995, pp. 159-163.
  472. J. Tao, N.W. Cheung, C. Hu, “Electromigration Characteristics of TiN Barrier Layer Material,” IEEE Electron Device Letters, Vol. 16, June 1995, pp. 230-232.
  473. Y.C. King, B. Yu, J. Pohlman, C. Hu, “Punchthrough Transient Voltage Suppressor for Low Voltage Electronics,” IEEE Electron Device Letters, Vol. 16, No. 7, July 1995, pp. 303-305.
  474. W.S. Choi, F. Assaderaghi, Y.J. Park, H.S. Min, C. Hu, R.W. Dutton, “Simulation of Deep Submicron SOI N-MOSFET Considering the Velocity Overshoot Effect,” IEEE Electron Device Letters, Vol. 16, No. 7, July 1995, pp. 333-335.
  475. J.B. Liu, S.K. Iyer, J. Min, P. Chu, R. Gronsky, C. Hu, N. Cheung, “Competitive Oxidation During Buried Oxide Formation Using Separation by Plasma Implantation of Oxygen,” Materials Research Society Symposium Proceedings, vol. 388, Film Synthesis and Growth, July/Aug 1995, pp. 385-391.
  476. G. Zhang, C. Hu, P.Y. Yu, S. Chiang, S. Eltoukhy, E.Z. Hamdy, “An Electro-Thermal Model for Metal-Oxide-Metal Antifuses,” IEEE Transaction on Electron Devices, Vol. 42, no. 8, August 1995, pp. 1548-1558.
  477. E.R. Minami, S.B. Kuusinen, E. Rosenbaum, P.K. Ko, C. Hu, “Circuit-Level Simulation of TDDB Failure in Digital CMOS Circuits,” IEEE Transactions on Semiconductor Manufacturing, Vol. 8, no. 3, August 1995, pp. 370-374.
  478. C. Hu, “BSIM3 MOSFET Model for Circuit Simulation,” Hierarchical Technology CAD Workshop, Stanford University, August 1995, pp. 8.1-8.16.
  479. K. Noda, T. Uchida, T. Tatsumi, C. Hu, “Hot-Carrier Reliability of 0.1mm Delta-Doped MOSFETs,” Extended Abstracts of 1995 International Conf. on Solid State Devices and Materials , August 1995, pp. 806-808.
  480. B. Yu, Y-C. King, C. Hu, J. Pohlman, “Punchthrough Transient Voltage Suppressor for EOS/ESD Protection of Low-Voltage IC’s,” IEEE Electrical Overstress/Electrostatic Discharge Symposium Proceedings, September 1995, pp. 34-42.
  481. Invited Paper, P. Pavan, R. Tu, E. Minami, G. Lum, P.K. Ko, C. Hu, “Simulating radiation reliability with BERT,”  Microelectronics Journal, Volume 26, Number 6, September 1995, pp. 627-633.
  482. M. Chan, S.S. Yuen, Z.J. Ma, K.Y. Hui, P.K. Ko, C. Hu, “ESD Reliability and Protection Schemes in SOI CMOS Output Buffers,” IEEE Transactions on Electron Devices, Vol. 42, no. 10, October 1995, pp. 1816-1821.
  483. Y.C. Shih, G. Zhang, C. Hu, W.G. Oldham, “Thin Dielectric Degradation during Silicon Selective Epitaxial Growth Process,” Applied Physics Letters , Vol. 67, No. 14, Oct. 2 1995, pp. 2040-2042.
  484. M. Chan, S. Fung, C. Hu, P.K. Ko, “A High Performance Lateral Bipolar Transistor from a SOI CMOS Process,” Proc. 1995 IEEE International SOI Conference , Oct. 1995, pp. 90-91.
  485. J.B. Liu, S.K. Iyer, J. Min, P.K. Chu, R. Gronsky, C. Hu, N.W. Cheung, “Synthesis of Buried Oxide by Plasma Implantation with Oxygen and Water Plasma,” Proc. 1995 IEEE International SOI Conference , Oct. 1995, pp. 166-167.
  486. J.B. Liu, S.K. Iyer, C. Hu, N. Cheung, R. Gronsky, J. Min, P. Chu, “Formation of Buried Oxide in Silicon Using Separation by Plasma Implementation of Oxygen,” Appl. Physics Letter , Vol. 67, No. 16, 16 October, 1995, pp. 2362-2363.
  487. H.C. Wann, C. Hu, “High-Endurance Ultra-Thin Tunnel Oxide in MONOS Device Structure for Dynamic Memory Application,” IEEE Electron Device Letters, Vol. 16, No. 11, Nov. 1995, pp. 491-493.
  488. J. Tao, N.W. Cheung, C. Hu, “Modeling Electromigration Lifetime under Bidirectional Current Stress,” IEEE Electron Device Letters , Vol. 16, No. 11, Nov. 1995, pp. 476-478.
  489. M. Chan, B. Yu, Z-J. Ma, C.T. Nguyen, C. Hu, P. K. Ko, “Comparative Study of Fully Depleted and Body-Grounded Non-Fully-Depleted SOI MOSFET’s for High Performance Analog and Mixed Signal Circuits,” IEEE Transaction Electron Devices, Vol. 42, No. 11, Nov. 1995, pp. 1975-1981.
  490. M. Chan, S. Fung, C. Hu, P.K. Ko, “A Novel SOI CBiCMOS Compatible Device structure for Analog and Mixed-Mode Circuits,” 1995 IEEE TENCON Proceedings, pp. 40-43, Nov. 1995.
  491. J.F. Chen, B.W. McGaughy, C. Hu, “Statistical Variation of NMOSFET Hot-Carrier Lifetime and its Impact on Digital Circuit Reliability,” International Electron Devices Meeting Technical Digest , Dec. 1995, pp. 29-32.
  492. G. Zhang, Y. King, S. Eltoukhy, E. Handy, T. Jing, P. Yu, C. Hu, “On-State Reliability of Amorphous Silicon Antifuse,” International Electron Devices Meeting Technical Digest , Dec. 1995, pp. 551-554.
  493. M. Chan, S.K. Fung, K.Y. Hui, C. Hu, P.K. Ko, “SOI MOSFET Design for All-Dimensional Scaling with Short Channel Narrow Width and Ultra-Thin Films,” International Electron Devices Meeting Technical Digest , Dec. 1995, pp. 631-634.
  494. C.H. Wann, C. Hu, “High Endurance Ultra-Thin Tunnel Oxide for Dynamic Memory Application,” International Electron Devices Meeting Technical Digest, Dec. 1995, pp. 867-870.
  495. Invited Paper, Y. Cheng, C. Hu, K. Chen, M. Chan, M-C. Jeng, Z. Liu, J. Huang, P.K. Ko, “A Unified BSIM I-V Model for Circuit Simulation,” Proc. 1995 International Semiconductor Device Research Symposium, Dec. 1995, pp. 603-606.
  496. K. Chen, J. Duster, H. Wann, T. Tanaka, M. Yoshida, P.K. Ko, C. Hu, “Universal MOSFET Carrier Mobility Model and Its Application in Device Modeling and Optimization,” Proc. 1995 International Semiconductor Device Research Symposium, Dec. 1995, pp. 607-610.
  497. K.B. Nguyen, G.F. Cardinale, D.A. Tichenor, G.D. Kubiak, A.K. Ray-Chaudhuri, Y. Perras, S.J. Haney, R. Nissen, K. Krenz, R.H. Stulen, H. Fujioka, C. Hu, J. Bokor, D.M. Tennant, L.A. Fetter, “Fabrication of Metal-Oxide-Semiconductor Devices with Extreme Ultraviolet Lithography,” J. Vac. Sci. Technol. B 14, 4188, 1996.
  498. K.B. Nguyen, G.F. Cardinale, D.A. Tichenor, K. Berger, A.K. Ray-Chaudhuri, Y. Perras, S.J. Haney, R. Nissen, K. Krenz, R.H. Stulen, H. Fujioka, C. Hu, J. Bokor, D.M. Tennant, L.A. Fetter, OSA Trends in Optics and Photonics Vol. 4, Extreme Ultraviolet Lithography, G.D. Kubiak and D.R. Kania, eds., Optical Society of America, Washington, DC, 1996, pp. 208-211.
  499. E. Rosenbaum, J.C. King, C. Hu, “Accelerated Testing of Si0 2 Reliability,” IEEE Trans. on Electron Devices, Vol. 43, No. 1, January 1996, pp. 70-80.
  500. K. Chen, H.C. Wann, J. Duster, D. Pramanik, S. Nariami, P.K. Ko, C. Hu, “An Accurate Semi-Empirical Saturation Drain Current Model for LDD N-MOSFET,” IEEE Electron Device Letters, Vol. 17, No. 3, March 1996, pp. 145-147.
  501. Invited Review, H.C. Shin, C. Hu, “Thin Gate Oxide Damage Due to Plasma Processing,” Semiconductor Science and Technology, Vol. 11, No. 4, April 1996, pp. 463-473.
  502. K. Chen, H.C. Wann, P.K. Ko, C. Hu, “The Impact of Device Scaling and Power Supply Changes on CMOS Gate Performance,” IEEE Electron Device Letters, Vol. 17, No. 5, May 1996, pp. 202-204.
  503. J. Tao, J.F. Chen, N.W. Cheung, C. Hu, “Modeling and Characterization of Electromigration Failures Under Bidirectional Current Stress,” IEEE Transactions on Electron Devices, Vol. 43, No. 5, May 1996, pp. 800-808.
  504. J. Tao, J.F. Chen, N.W. Cheung, C. Hu, “Electromigration Design Rules for Bidirectional Current,” International Reliability Symposium Proceedings, May 1996, pp. 180-187.
  505. K. Banerjee, A. Amerasekera, C. Hu, “Characterization of VLSI Circuit Interconnect Heating and Failure under ESD Conditions,” International Reliability Physics Symposium Proceedings, May 1996, pp. 237-245.
  506. S. Zheng, D. Park, N. Bui, C. Hu, J. Yue, “A Quick Experimental Technique in Estimating the Cumulative Plasma Charging Current with MOSFET and Determining the Reliability of the Protection Diode in the Plasma Ambient,” 1996 First International Symposium on Plasma Process-Induced Damage Proceedings, May 1996, p. 27-29.
  507. Y. Cheng, M. Jeng, Z. Liu, K. Chen, M. Chen, C. Hu, P.K. Ko, “An Investigation of the Robustness, Accuracy and Simulation Performance of a Physics-Based Deep-Submicrometer BSIM Model for Analog/Digital Circuit Simulation,” IEEE 1996 Custom Integrated Circuits Conference Proceedings, May 1996, pp. 321-324.
  508. Banquet Speech: C. Hu, “Semiconductor Technology in the Next 35 Years,” 1996 Semiconductor Technology CAD Workshop, Hsinchu, Taiwan, May 14-15, 1996.
  509. N. Lindert, M. Yoshida, H. Wann, C. Hu, “Comparison of GIDL in p +- poly and n + – poly PMOS Devices,” IEEE Device Letters, Vol. 17, No. 6, June 1996, pp. 285-287.
  510. C. Wann, R. Tu, B. Yu, C. Hu, K. Noda, T. Tamaka, M. Yoshida, K. Hui, “A Comparative Study of Advanced MOSFET Structures,” 1996 Symposium of VLSI Technology Digest, June 1996, pp. 32-33.
  511. B. Yu, E. Nowak, K. Noda, C. Hu, “Reverse Short-channel Effects and Channel Engineering in Deep-Submicron MOSFETs,” 1996 Symposium of VLSI Technology Digest, June 1996, pp. 162-163.
  512. K. Banerjee, L. Ting, N. Cheung, C. Hu, “Impact of High Current Stress Conditions on VLSI Interconnect Electromigration Reliability Evaluation, Proceedings of 13th VLSI Multilevel Interconnection Conference (VMIC) , June 1996, pp. 289-294.
  513. B. Yu, G. Zhang, C. Hu, Z-J. Ma, “Hot-Carrier Effect in Ultra-Thin-Film Fully-Depleted SOI MOSFETs,” IEEE 54th Device Research Conference Digest , June 1996, pp. 22-23.
  514. D. Park, C. Hu, “Enhanced Ion Implantation Charging Damage on Thin Gate Oxide Due to Photoresist,” Proc. of Eleventh International Conf. on Ion Implantation Technology , June 1996, pp. 93-95.
  515. K. Imai, C. Hu, T. Andoh, Y. Kinoshita, Y. Matsubara, T. Tatsumi, T. Yamazaki, “0.15 /spl mu/m Delta-Doped CMOS with On-Field Source/Drain Contacts,” 1996 Symposium on VLSI Technology, 1996 Digest of Technical Papers, pp. 172-173, June 1996.
  516. R. Nagisetty, C. Hu, “A Novel Self-Aligned Punchthrough Implant,” IEEE Transactions on Electron Devices , Vol. 43, No. 8, August 1996, pp. 1312-1314.
  517. K. Banerjee, S. Rzepka, A. Amerasekera, C. Hu, “Characterization and Simulation of Self-Healing in Multi-Level VLSI Interconnect,” Techcon 96 , September 1996, p. 25.
  518. K. Chen, Y. Cheng, C. Hu, “Experimental Confirmation of a Semi-Empirical Unified Channel Carrier Density Model for MOSFET Modeling,” Techcon 96 , September 1996, p. 69.
  519. Y. Cheng, M. Jeng, Z. Liu, J. Huang, K. Chen, C. Hu, “A Study of Deep-Submicron MOSFET Technology Prediction and Scaling with BSIM3,” Techcon 96 , September 1996, p. 130.
  520. K. Chen, J. Huang, J. Duster, P.K. Ko, C. Hu, “MOSFET Electron Mobility Model of Wide Temperature Range (77-400K) for IC Simulation,” Techcon 96 , September 1996, p. 214.
  521. Best Paper Award, B.W. McGaughy, J. F. Chen, C. Hu, “Statistical Hot-Carrier Reliability Simulation for Digital Circuits,” Techcon 96 , September 1996, p. 227
  522. C.H. Wann, K. Noda, T. Tanaka, M. Yoshida, C. Hu, “A Comparative Study of Advanced MOSFET Concepts,” IEEE Transactions on Electron Devices , Vol. 43, No. 10, October 1996, pp. 1742-1753.
  523. B. Yu, T. Tanaka, C. Hu, “Modeling Off-State Leakage Current of DG-SOI MOSFETs,” Proc. 1996 IEEE International SOI Conf. , October 1996, pp. 15-17.
  524. J. F. Chen, C. Gelatos, P. Tobin, R. Shimer, and C. Hu, “Reverse Antenna Effect Due to Process-Induced Quasi-Breakdown of Gate Oxide,” 1996 IEEE International Integrated Reliability Workshop Final Report , Lake Tahoe, CA, pp. 94-97, October 20-23, 1996.
  525. K. Banerjee, S. Rzepka, A. Amerasakera, N. Cheung, and C. Hu, “Thermal Analysis of the Fusion Limits of Metal Interconnect under Short Duration Current Pulses,” 1996 IEEE International Integrated Reliability Workshop Final Report , Lake Tahoe, CA, pp. 98-102, October 20-23, 1996.
  526. X. Lu, S.S.K. Iyer, J. Min, Z. Fan, J.B. Lin, P.K. Chu, C. Hu, N. Cheung, “SOI Material Technology Using Plasma Immersion Ion Implementation,” Proc. 1996 IEEE International SOI Conf. , October 1996, pp. 48-49.
  527. Keynote Invited Paper, C. Hu, “AC Effects in IC Reliability,” Proceedings of the 17th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis , October 1996, pp. 1611-1617.
  528. K. Chen, C. Hu, “A Model of CMOS Gate Delay and Projection of Future Trends,” 1996 2nd International Conference on ASIC (ASICON ’96) Proceedings, Session 5.6, pp. 436-439, Shanghai, China, October 1996.
  529. H. Fujioka, C. Wann, C. Hu, “Characterization of MOS Structures with Ultra-Thin Tunneling Oxynitride,” Materials Research Society Symposium , Vol. 405, pp. 333-337, 1996.
  530. J. Tao, N.W. Cheung, C. Hu, “Characterization and Modeling of Electromigration Failures in Multilayered Interconnects and Barrier Layer Materials,” IEEE Trans. on Electron Devices , Vol. 43, No. 11, November 1996, pp. 1819-1825.
  531. Y.C. King, B. Yu, J. Pohlman, C. Hu, “Punchthrough Diode as the Transient Voltage Suppression for Low-Voltage Electronics,” IEEE Trans. on Electron Devices , Vol. 43, No. 11, November 1996, pp. 2037-2040.
  532. Invited Commemorative Paper, C. Hu, “Circuit Level Reliability Simulation Technology,” Proceedings of the 6th Reliability Center of Japan (MITI) Reliability Symposium , Tokyo, Japan, November 1996, pp. 27-30.
  533. Y. Cheng, M-C. Jeng, Z. Liu, K. Chen, B. Yu, K. Imai, C. Hu, “Quarter-Micrometer Surface and Buried Channel PMOSFET Modeling for Circuit Simulation,” Semiconductor Science and Technology , Vol. 11, pp. 1763-1769, November 1996.
  534. H. Koinuma, H. Fujioka, C. Hu, T. Koida, M. Kawasaki, “Structure and Numerical Simulation of Field Effect Solar Cell,” Materials Research Society Symposium Proceedings , Vol. 426, pp. 95-100, 1996.
  535. K.B. Nguyen, G.F. Gardinale, D.A. Tichenor, H. Fujioka, C. Hu, J. Bokor, D.M. Tennant, “Fabrication of Metal-Oxide-Semiconductor Devices with Extreme Ultraviolet Lithography,” Journal of Vacuum Science & Technology , Vol. B14(6), pp. 4188-4192, November/December 1996.
  536. B. Yu, Z-J. Ma, G. Zhang, C. Hu, “Hot-Carrier-Induced Degradation in Ultra-Thin-Film Fully-Depleted SOI MOSFETs,” Solid State Electronics , Vol. 39, No. 12, pp. 1791-1794, December 1996.
  537. K. Banerjee, A. Amerasekera, G. Dixit, C. Hu, “The Effect of Interconnect Scaling and Low-K Dielectric on the Thermal Characteristics of the IC Metal,” Technical Digest of International Electron Device Meeting , pp. 65-68, December 1996.
  538. J. Chen, B. McGaughy, D. Sylvester, C. Hu, “An On-Chip Attofarad Interconnect Change-Based Capacitance Measurement (CBCM) Technique,” Technical Digest of International Electron Devices Meeting , pp. 69-72, December 1996.
  539. C. Wann, F. Assaderaghi, R Dennard, C. Hu, G. Shahidi, Y. Tan, “Channel Profile Optimization and Device Design for Low Power, High Performance Dynamic-Threshold MOSFET,” Technical Digest of International Electron Devices Meeting , pp. 113-116, December 1996.
  540. Invited Paper, C. Hu, “Gate Oxide Scaling Limits and Projection,” Technical Digest of International Electron Devices Meeting , pp. 319-322, December 1996.
  541. J. Chen, C. Hu, D. Wan, P. Bendix, A. Kapoor, “E-T Based Statistical Modeling and Compact Statistical Circuit Simulation Methodologies,” Technical Digest of International Electron Devices Meeting , pp. 635-638, December 1996.
  542. D. Park, C. Hu, S. Zheng, N. Bui, “A Full-Process Damage Detection Method Using Small MOSFET and Protection Diode,” IEEE Electron Device Letters , Vol. 17, No. 12, pp. 563-565, December 1996.
  543. K.B. Nguyen, G.F. Gardinale, H. Fujioka, C. Hu, J. Bokor, D.M. Tennant, L.A. Fetter, “Fabrication of MOS Devices with Extreme Ultraviolet Lithography,” Extreme Ultraviolet Lithography , Vol. 4, Optical Society of America, pp. 208-211, 1996.
  544. B. W. McGaughy, J.C. Chen, D. Sylvester, C. Hu, “A Simple Method for On-Chip Sub-Femto Farad Interconnect Capacitance Measurement,” IEEE Electron Device Letters , Vol. 18, No. 1, pp. 21-23, January 1997.
  545. Keynote Paper, C. Hu, “Advanced MOSFET Comparison,” Sematech Front End of Line Processes and Devices Workshop, Dallas, TX, pp. 11-32, January 9-10, 1997.
  546. D. Sinitsky, R. Tu, C. Liang, M. Chan, J. Bokor, and C. Hu, “AC Output Conductance of SOI MOSFETs and Impact on Analog Applications,” IEEE Electron Device Letters , Vol. 18, No. 2, pp. 36-38, February 1997.
  547. D. Sinitsky, F. Assaderaghi, C. Hu, and J. Bokor, “High Field Hole Velocity and Velocity Overshoot in Silicon Inversion Layers,” IEEE Electron Device Letters , vol. 18, no. 2, pp. 54-56, February 1997.
  548. Y. Cheng, M-C. Jeng, Z. Liu, J. Huang, M. Chan, K. Chen, P. K. Ko, and C. Hu, “A Physical and Scalable I-V Model in BSIM3v3 for Analog/Digital Circuit Simulation,” IEEE Trans. on Electron Devices , Vol. 44, No. 2, pp. 277-287, February 1997.
  549. F. Assaderaghi, D. Sinitsky, S. Parke, J. Bokor, P. K. Ko, and C. Hu, “Dynamic Threshold-Voltage MOSFET (DTMOS) for Ultra-Low Voltage VLSI,” IEEE Trans. on Electron Devices , Vol. 44, No. 3, pp. 414-422, March 1997.
  550. J.C. Chen, D. Sylvester, C. Hu, H. Aoki, S. Nakagawa, S.Y. Oh, “An On-Chip, Interconnect Capacitance Characterization Method with Sub-Femto-Farad Resolution,” IEEE International Conference on Microelectronic Test Structures (ICMTS), Proceedings, pp. 77-80, March 1997.
  551. B. Yu, C. H. J. Wann, E. D. Novak, K. Noda, and C. Hu, “Short-Channel Effect Improved by Lateral Channel-Engineering in Deep-Submicronmeter MOSFETs,” IEEE Trans. on Electron Devices , Vol. 44, No. 4, pp. 627-634, April 1997.
  552. F. Assaderaghi, D. Sinitsky, J. Bokor, P. K. Ko, H. Gaw, and C. Hu, “High-Field Transport of Inversion-Layer Electrons and Holes Including Velocity Overshoot,” IEEE Trans. on Electron Devices , Vol. 44, No. 4, pp. 664-671, April, 1997.
  553. K. Banerjee, A. Amerasekera, G. Dixit, N. Cheung, and C. Hu, “Characterization of Contact and Via Failure under Short Duration High Pulsed Current Stress,” Proc. 35th IEEE International Reliability Physics Symposium , pp. 216-222, April 1997.
  554. K. Chain, J.H. Huang, J. Duster, P.K. Ko, and C. Hu, “A MOSFET Electron Mobility Model of Wide Temperature Range for IC Simulation,” Semiconductor Science and Technology , pp. 355-358, April 1997.
  555. K. Banerjee, A. Amerasekera, N. Cheung, C. Hu, “Failure Mechanisms of Multi Layered Thin Film Metal Interconnects Under a High Current Pulse,” MRS Spring Symposium, San Francisco, CA, April 1997.
  556. C. Shih, R. Lambertson, F. Hawley, F. Issaq, J. McCollum, E. Hamdy, H. Sakurai, H. Yuasa, H. Honda, T. Yamaoka, T. Wada, C. Hu, “Characterization and Modeling of a Highly Reliable Metal-to-Metal Antifue for High-Performance and High-Density Field-Programmable Gate Arrays,” Proceedings of 1997 Reliability Physics Symposium, pp. 25-33, April 1997.
  557. D. Park, C. Hu, “Plasma Charging Damage on Ultra-Thin Gate Oxides,” Proc. 2nd International Symposium on Plasma Process Induced Damage , pp. 15-19, May 1997.
  558. D. Sylvester, J. Chen, C. Hu, “Investigation of Interconnect Capacitance Characterization Using Charge-Based Capacitance Measurement (CBCM) Technique and 3-D Simulation,” IEEE 1997 Custom Integrated Circuits Conference Proc., pp. 491-494, May 1997.
  559. B. Yu, D-H. Ju, N. Keppler, T-J.. King, C. Hu, “Gate Engineering for Performance and Reliability in Deep-Submicron CMOS Technology,” 1997 Symposium on VLSI Technology Digest , pp. 105-106, June 1997.
  560. K. Chen, C. Hu, P. Fang, A. Gupta, M.R. Lin, D. Wollesen, “Experimental and Analytical Study of CMOS Scaling in Deep Submicron Regime Including Quantum and Polysilicon Gate Depletion Effects,” 55th Device Research Conference Digest , pp. 20-21, June 1997.
  561. B. Yu, C. Hu, K. Imai, “Characterization of Inversion Layer Carrier Profile in Deep-Submicron PMOSFETs,” 55th Device Research Conference Digest , pp. 22-23, June 1997.
  562. Y-C. King, H. Fujioka, S. Kamohara, W-C. Lee, C. Hu, “AC Charge Centroid Model for Quantization of Inversion Layer in n-MOSFET,” International Symposium on VLSI Tech., Systems, and Applications Proc. , pp. 245-249, June 1997.
  563. B. Yu, W-C. Lee, C. Hu, “Modeling Short-Channel Effects of CMOSFETs with Channel Engineering, Defect Enhanced Diffusion, and Gate Depletion,” International Symposium on VLSI Tech., Systems, and Applications, pp. 298-302, June 1997.
  564. D. Sinitsky, F. Assaderaghi, M. Orshansky, J. Bokor, C. Hu, “An Extension of BSIM3 Model Incorporating Velocity Overshoot,” International Symposium on VLSI Tech., Systems, and Applications , pp. 307-310, June 1997.
  565. R. Tu, D. Sinitsky, F. Assaderaghi, C. Wann, C. Hu, “Simulation of Floating Body Effect in SOI Circuits Using BSIM3SOI,” 1997 International  Symposium on VLSI Technology,  Systems, and Applications, Proceedings of Technical Papers, pp. 339-342, June, 1997.
  566. B. Yu, D-H. Ju, N. Kepler, C. Hu, “Impact of Nitrogen Implantation into Polysilicon Gate on High Performance Dual-Gate CMOS Transistors,” IEEE Electron Device Letters , Vol. 18, No. 7, pp. 312-314, July 1997.
  567. D. Sinitsky, F. Assaderaghi, M. Orshansky, J. Bokor, C. Hu, “Velocity Overshoot of Electrons – Holes in Si Inversion Layers,” Solid State Electronics , Vol. 41, No. 8, pp. 1119-1125, August 1997.
  568. K. Chen, C. Hu, “Device and technology optimizations for low power design in deep sub-micron regime,” 1997 International Symposium on Low Power Electronics and Design (ISLPED ’97) , Monterey, August 1997.
  569. K. Chen, C. Hu, P. Fang, A. Gupta, M. Lin, D. Wollesen, “Accurate Models for CMOS Scaling in Deep Submicron Regime,” 1997 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD ’97) , Boston, September 1997.
  570. K. Banerjee, A. Amerasekera, N. Cheung, C. Hu, “High-Current Failure Model for VLSI Interconnects Under Short-Pulse Stress Conditions,” IEEE Electron Device Letters , Vol. 18, No. 9, pp. 405-407, September 1997.
  571. R. Tu, J.C. King, H. Shin, C. Hu, “Simulating Process-Induced Gate Oxide Damage in Circuits,” IEEE Electron Device Letters , Vol. 44, No. 9, pp. 1393-1400, September 1997.
  572. H. Shin, M. Je, C. Hu, “Overestimation of Oxide Defects Density in Large Test Capacitors Due to Plasma Processing,” IEEE Electron Device Letters , Vol. 44, No. 9, pp. 1554-1556, September 1997.
  573. K. Chen, C. Hu, P. Fang, M.R. Lin, D.L. Wollesen, “Optimizing Quarter and Sub-Quarter Micron CMOS Circuit Speed Considering Interconnect Loading Effects,” IEEE Electron Device Letters , Vol. 44, No. 9, pp. 1556-1558, September 1997.
  574. S. Rzepka, K. Banerjee, E. Meusel, and C. Hu, “Characterization of Self-Heating in Advanced VLSI Interconnect Lines Based on Thermal Finite Element Simulation,” 3rd THERMINIC Workshop , pp. 108-113, September, 1997.
  575. B. Yu, D-H. Ju, N. Kepler, T-J. King, C. Hu, “Impact of Gate Microstructure on Complementary Metal-Oxide-Semiconductor Transistor Performance,” Japanese Journal of Applied Physics , Vol. 36, Part 2, No. 9A/B, pp. L1150-1152, September 1997.
  576. C.-C. Shih, R. Lambertson, F. Hawley, F. Issaq, J. McCollum, E. Hamdy, H. Sakurai, H. Yuasa, H. Honda, T. Yamaoka, T. Wada, and C. Hu, “Characterization and Modeling of a Highly Reliable Metal-to-Metal Antifuse for High-Performance and High-Density Field-Programmable Gate Arrays,” IEEE Trans. on Electron Devices , Vol. 44, No. 4, pp. 25-30, September 1997.
  577. Invited Paper, C. Hu, “Reliability and Scaling of Thin Gate Oxide,” Extended Abstracts of the 1997 International Conference on Solid State Devices and Materials, Hamamatsu , pp. 6-7, September 1997.
  578. H. Fujioka, K. Ono, Y. Sato, C. Hu, M. Oshima, “Simulations of 2-Dimensional Hole Gas for PMOS devices with Phosphorus Pile-up,” Extended Abstracts of the 1997 International Conference on Solid State Devices and Materials, Hamamatsu , pp. 508-509, September 1997.
  579. S. Sundar Kumar Iyer, X. Lu, J. Liu, J. Min, Z. Fan, P. Chu, C. Hu, “Separation by Plasma Implantation of Oxygen (SPIMOX) Operational Phase Space,” IEEE Trans. on Plasma Science , Vol. 25, pp. 1128-1135, October 1997.
  580. Invited Paper, C. Hu, “Berkeley Reliability Simulator-BERT,” SRC Topical Research Conference on Reliability, Nashville, TN, October 1997.
  581. Invited Paper, K. Banerjee, A. Amerasekera, G. Dixit, C. Hu, “High Current Effects in Metal Interconnects,” SRC Topical Research Conference on Reliability, Nashville, TN, October 1997.
  582. S. Kamohara, Y-C. King, K. Chen, D. Park, C. Hu, “MOSFET Carrier Mobility Model Based on the Density-of-State at the DC Centroid in the Quantized Inversion Layer,” 5th International Conference on VLSI and CAD, pp. 171-173, October 1997.
  583. B. Yu, T.J. King, C. Hu, D.H. Ju, N. Kepler, “CMOS Transistor Reliability and Performance Impacted by Gate Microstructure,” Integrated Reliability Workshop Final Report, 1997 IEEE International, pp. 35-41, October 1997.
  584. K. Chen, C. Hu, P. Fang, M.R. Lin, D.L. Wollesen, “Predicting CMOS Speed with Gate Oxide and Voltage Scaling and Interconnect Loading Effects,” IEEE Trans. on Electron Devices , Vol. 44, No. 11, pp. 1951-1957, November 1997.
  585. Y. Cheng, K. Imai, M-C. Jeng, Z. Liu, K. Chen, C. Hu, “Modelling Temperature Effects of Quarter Micrometre MOSFETs in BSIM3v3 for Circuit Simulation,” Semiconductor Science and Technology , Vol. 12, No. 11, pp. 1349-1354, November 1997.
  586. B. Yu, K. Imai, C. Hu, “Electrical Characterization of Inversion Layer Carrier Profile in Deep-Submicron p-MOSFETs,” Semiconductor Science and Technology , Vol. 12, No. 11, pp. 1355-1357, November 1997.
  587. A. Gupta, P. Fang, M. Song, M-R. Lin, D. Wollesen, K. Chen, C. Hu, “Accurate Determination of Ultrathin Gate Oxide Thickness and Effective Polysilicon Doping of CMOS Devices,” IEEE Electron Device Letters , Vol. 18, No. 12, pp. 580-582, December 1997.
  588. K. Banerjee, A. Amerasekera, G. Dixit, C. Hu, “Temperature and Current Effects on Small-Geometry-Contact Resistance,” 1997 IEDM Technical Digest , pp. 115-118, December 1997.
  589. S. Yamamichi, A. Yamamichi, D. Park, C. Hu, “Impact of Time Dependent Dielectric Breakdown and Stress Induced Leakage Current on the Reliability of (Ba,Sr)TiO3 Thin Film Capacitors for Gbit-scale DRAMs,” 1997 IEDM Technical Digest , pp. 261-264, December 1997.
  590. Best Student Paper Award,D. Sylvester, J. Chen, C. Hu, “Measurement-Based Interconnect Capacitance Characterization for Circuit Simulations,” 1997 International Semiconductor Device Research Symposium , pp. 67-70, December 1997.
  591. B. Yu, E. Nowak, T. Sugii, C. Hu, “Lateral Channel Engineering in VLSI CMOS FET’s,” 1997 International Semiconductor Device Research Symposium , pp. 99-102, December 1997.
  592. N. Lindert, S. Tang, T. Sugii, C. Hu, “Breaking the 1V Barrier: Dynamic Threshold Logic for a Wide Range of Supply Voltages Down to 0.3V,” 1997 International Semiconductor Device Research Symposium , pp. 103-106, December 1997.
  593. W. Liu, C. Hu, L. Liu, X. Li, “Simulation of 0.5V Bulk DT-MOSFET’s with Sub-0.1m Gate Length: Device Structures, Characteristics and Circuit Performance,” 1997 International Semiconductor Device Research Symposium , pp. 219-222, December 1997.
  594. W. Liu, M. Orshansky, X. Jin, K. Chen, C. Hu, “MOSFET Intrinsic-Capacitance Related Inaccuracy in CMOS Circuit Speed Simulation,” 1997 International Semiconductor Device Research Symposium , pp. 337-340, December 1997.
  595. S. Fung, M. Chan, D. Sinitsky, S. Tang, C. Hu, P. Ko, “Analysis of Floating Body Effect in Non-fully Depleted SOI MOSFET’s based on Capacitive Coupling,” 1997 International Semiconductor Device Research Symposium , pp. 359-362, December 1997.
  596. Best Student Paper Award, W-C. Lee, A. Wang, T-J. King, C. Hu, “Impact of Poly-Si0.8Ge0.2-Gate Technology on Device Performance and Reliability,” 1997 International Semiconductor Device Research Symposium , pp. 513-516, December 1997.
  597. X. Jin, W. Liu, K. Chen, Y. King, J. Tao, C. Hu, “Charge Thickness Model – A Novel and Accurate Compact C-V Model for 2.5nm Gate Oxide Technology and Beyond,” 1997 International Semiconductor Device Research Symposium , pp. 529-532, December 1997.
  598. B. Yu, Y-J. Tung, S. Tang, E. Hui, T-J. King, C. Hu, “Ultra-Thin-Body Silicon-On_Insulator MOSFET’s for Terabit-Scale Integration,” 1997 International Semiconductor Device Research Symposium , pp. 623-626, December 1997.
  599. D. Park, C. Hu, “Plasma Charging Damage on Ultrathin Gate Oxides,” IEEE Electron Device Letters, Vol. 19, No. 1, pp. 1-3, January 1998.
  600. Review Paper, C. Hu, “Reliability Phenomena Under AC Stress,” Microelectronic Reliability , Vol. 38, No. 1, pp. 1-5, January 1998.
  601. J. Chen, M. Orshansky, C. Hu, C-P. Wan, “Statistical Circuit Characterization for Deep-Submicron CMOS Designs,” 1998 IEEE International Solid-State Circuits Conference, February 1998.
  602. D. Sylvester, J. Chen, C. Hu, “Investigation of Interconnect Capacitance Characterization Using Charge-Based Capacitance Measurement (CBCM) Technique and Three-Dimensional Simulation,” IEEE Journal of Solid-State Circuits , Vol. 33, No. 3, pp. 449-453, March 1998.
  603. Invited Paper, J. Tao, B-K. Liew, J. Chen, N. Cheung, C. Hu, “Electromigration Under Time-Varying Current Stress,” Microelectronics Reliability, Vol. 38, No. 3, pp. 295-308, March 1998.
  604. S. Kamohara, D. Park, C. Hu, “Deep-Trap SILC (Stress Induced Leakage Current) Model for Nominal and Weak Oxides,” 36th Annual Reliability Physics Symposium Proceedings, 1998 IEEE International, pp. 57-61, March 1998.
  605. K. A. Anselm, H. Nie, C. Hu, C. Lenox, P. Yuan, G. Kinsey, J. C. Campbell, and B. G. Streetman, “Performance of Thin Separate Absorption, Charge, and Multiplication Avalanche Photodiodes,” IEEE Journal of Quantum Electronics, Vol. 34, No. 3, pp. 482-490, March 1998.
  606. H. Nie, K. A. Anselm, C. Lenox, P. Yuan, C. Hu, G. Kinsey, B. G. Streetman, and J. C. Campbell, “Resonant-Cavity Separate Absorption, Charge and Multiplication Avalanche Photodiodes With High-Speed and High Gain?Bandwidth Product,” IEEE Phontonics Technology Letters, pp. 409-411, Vol. 10, No. 3, March 1998.
  607. K. Noda, T. Tatsumi, T. Uchida, K. Nakajima, H. Miyamoto, C. Hu, “A 0.1m Delta-Doped MOSFET Fabricated with Post-Low-Energy Implanting Selective Epitaxy,” IEEE Transactions on Electron Devices , Vol. 45, No. 4, pp. 809-814, April 1998.
  608. M. Chan, K. Hui, C. Hu, P. Ho, “A Robust and Physical BSIM3 Non-Quasi-Static Transient and AC Small-Signal Model for Circuit Simulation,” IEEE Transactions on Electron Devices , Vol. 45, No. 4, pp. 834-841, April 1998.
  609. K. Banerjee, A. Amerasekera, J.A. Kittl, C. Hu, “High Current Effects in Silicide Films for Sub-0.25 Micron VLSI Technologies,” IEEE International Reliability Physics Symposium Proceedings, pp. 284-292, April 1998.
  610. Invited Paper, S. Yamamichi, A. Yamamichi, D. Park, H. Yabuta, T-J. King, C. Hu, “Reliability Study on High Dielectric Constant (Ba,Sr) Ti03 Thin Film,” 193rd Electrochemical Society (ECS) Meeting, Meeting Abstracts, Vol. 98-1, Abstract No. 151, May 1998.
  611. J. Chen, D. Sylvester, C. Hu, “An On-Chip, Interconnect Capacitance Characterization Method with Sub-Femto-Farad Resolution,” IEEE Transactions on Semiconductor Manufacturing, Vol. 11, No. 2, pp. 204-210, May 1998.
  612. P. Fang, J. Tao, J.F. Chen, C. Hu, “Design in Hot-Carrier Reliability for High Performance Logic Applications,” IEEE 1998 Custom Integrated Circuits Conference, pp. 525-532, May 1998.
  613. J.F. Chen, J. Tao, P. Fang, C. Hu, “Performance and Reliability of Asymmetric LDD Devices and Logic Gates,” IEEE 1998 Custom Integrated Circuits Conference, pp. 533-536, May 1998.
  614. Keynote Address, C. Hu, “Device Technology After 2010,” International Symposium on Computing and Microelectronics, Peking University, pp. 29-33, May 1998.
  615. B. Yu, D-H. Ju, W-C. Lee, N. Kepler, T-J. King, C. Hu, “Gate Engineering for Deep-Submicron CMOS Transistors,” IEEE Transactions on Electron Devices, Vol. 45, No. 6, pp. 1253-1262, June 1998.
  616. D. Park, M. Kennard, Y. Melaku, N. Benjamin, T-J. King, C. Hu, “Stress-Induced Leakage Current Due to Charging Damage:  Gate Oxide Thickness and Gate Poly-Si Etching Condition Dependence,” 1998 3rd International Symposium on Plasma Process-Induced Damage, pp. 56-59, June 1998.
  617. D. Sylvester, C. Hu, O. S. Nakagawa, S-Y. Oh, “Interconnect Scaling: Signal Integrity and Performance in Future High-Speed CMOS Designs,” 1998 Symposium on VLSI Technology, pp. 42-43, June 1998.
  618. J-J. Ou, X. Jin, I. Ma, C. Hu, P. R. Gray, “CMOS RF Modeling for GHz Communication IC’s,” 1998 Symposium on VLSI Technology, pp. 94-95, June 1998.
  619. D. Sinitsky, S. Fung, S. Tang, P. Su, M. Chan, P. Ko, C. Hu, “A Dynamic Depletion SOI MOSFET Model for SPICE,” 1998 Symposium on VLSI Technology, pp. 114-115, June 1998.
  620. W-C. Lee, T-J. King, C. Hu, “Optimized Poly-Si1-xGex-Gate Technology for Dual Gate CMOS Application,” 1998 Symposium on VLSI Technology, pp. 190-191, June 1998.
  621. Keynote Address, C. Hu, “Silicon Nanoelectronics for the 21st Century,” IEEE Silicon Nanoelectronics Workshop Abstract, p. 1, June 1998.
  622. M. Orshansky, J.C. Chen, C. Hu, “A Statistical Performance Simulation Methodology for VLSI Circuits,” 35th Annual Design Automation Conference, pp. 402-407, June 1998.
  623. M. Orshansky, J.C. Chen, C. Hu, D. Wan, P. Bendix, “Approaches to Statistical Circuit Analysis for Deep Sub-Micron Technologies,” 1998 3rd International Workshop on Statistical Metrology, pp. 6-9, June 1998.
  624. M. Orshansky, D. Sinitsky, P. Scrobohaci, J. Bokor, C. Hu, “Impact of Velocity Overshoot, Polysilicon Depletion, and Inversion Layer Quantization on NMOSFET Scaling,” 56th Annual Device Research Conference, pp. 18-19, June 1998.
  625. W-C. Lee, Y-C. King, T-J. King, C. Hu, “Investigation of Poly-Si1-xGex for Dual-Gate CMOS Technology,” IEEE Electron Device Letters, Vol. 19, No. 7, pp. 247-249, July 1998.
  626. J.F. Chen, J. Tao, P. Fang, C. Hu, “0.35-um Asymmetric and Symmetric LDD Device Comparison Using a Reliability/Speed/Power Methodology,” IEEE Electron Device Letters, Vol. 19, No. 7, pp. 216-218, July 1998.
  627. C. Hu, D. Park, Y-C. King, “Thin Gate Oxides Promise High Reliability,” Semiconductor International, Vol. 21, No. 8, pp. 215-222, July 1998.
  628. Y-C. King, H. Fujioka, S. Kamohara, K. Chen, C. Hu, “DC Electrical Oxide Thickness Model for Quantization of the Inversion Layer in MOSFETs,” Semiconductor Science and Technology, Vol. 13, No. 8, pp. 963-965, August 1998.
  629. Y. Cheng, K. Chen, K. Imai, C. Hu, “A Unified MOSFET Channel Charge Model for Device Modeling in Circuit Simulation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 8, pp. 641-644, August 1998.
  630. Q. Xu, C. Hu, “New Ti-SALICIDE Process Using Sb and Ge Preamorphization for Sub-0.2 mm CMOS Technology,” IEEE Transactions on Electron Devices, Vol. 45, No. 9, September 1998.
  631. D. Sinitsky, S. Tang, A. Jangity, F. Assaderaghi, G. Shahidi, C. Hu, “Simulation of SOI Devices and Circuits Using BSIM3SOI,” IEEE Electron Device Letters, Vol. 19, No. 9, pp. 323-325, September 1998.
  632. J.F. Chen, K. Ishimaru, C. Hu, “Enhanced Hot-Carrier Induced Degradation in Shallow Trench Isolated Narrow Channel PMOSFET’s,” IEEE Electron Device Letters, Vol. 19, No. 9, pp. 332-334, September 1998.
  633. Q. Lu, D. Park, A. Kalnitsky, C. Chang, C-C. Cheng, S.P. Tay, T-J. King, C. Hu, “Leakage Current Comparison Between Ultra-Thin Ta205 Films and Conventional Gate Dielectrics,” IEEE Electron Device Letters, Vol. 19, No. 9, pp. 341-342, September 1998.
  634. S. Rzepka, K. Banerjee, E. Meusel, C. Hu, “Characterization of Self-Heating in Advanced VLSI Interconnect Lines Based on Thermal Finite Element Simulation,” IEEE Transactions on Components, Packaging, and Manufacturing Technology Part A,” Vol. 21, No. 3, pp. 406-411, September 1998.
  635. K. Banerjee, A. Amerasekera, G. Dixit, C. Hu, “A New Quantitative Model for Deep Sub-micron Contact Resistance,” Proceedings of the TECHCON, Las Vegas, September 1998.
  636. K. Chen, C. Hu, “Performance and Vdd Scaling in Deep Submicrometer CMOS,” IEEE Journal of Solid-State Circuits, Vol. 33, No. 10, pp. 1586-1589, October 1998.
  637. Invited Paper,Q. Xu, C. Hu, “Novel Ti-Salicide Process with Low Resistivity for Sub-0.2 mm CMOS Technology,” 1998 5th International Conference on Solid-State and Integrated Circuit Technology Proceedings, pp. 47-51, October 1998.
  638. Plenary Paper, C. Hu, “SOI and Device Scaling,” 1998 IEEE International SOI Conference Proceedings, pp. 1-4, October 1998.
  639. D. Park, Y-C. King, Q. Lu, T-J. King, C. Hu, “Transistor Characteristics with Ta2O5 Gate Dielectric,” IEEE Electron Device Letters, Vol. 19, No. 11, pp. 441-443, November 1998.
  640. Keynote Presentation, C. Hu, “IC Device Technology for the Next Century,” SEMICON Taiwan 98, pp. 1-10, November 1998.
  641. Y-C. King, T-J. King, C. Hu, “MOS Memory Using Germanium Nanocrystals Formed by Thermal Oxidation of Si1-xGex,” International Electron Devices Meeting Technical Digest, pp. 115-118, December 1998.
  642. D. Park, Q. Lu, T-J. King, C. Hu, A. Kalnitsky, S-P. Tay, C-C. Cheng, “SiON/Ta2O5/TiN Gate-Stack Transistor with 1.8nm Equivalent SiO2 Thickness,” International Electron Devices Meeting Technical Digest, pp. 381-384, December 1998.
  643. M. Krishnan, Y-C. Yeo, Q. Lu, T-J. King, J. Bokor, C. Hu, “Remote Charge Scattering in MOSFETs with Ultra-Thin Gate Dielectrics,” International Electron Devices Meeting Technical Digest, pp. 571-574, December 1998.
  644. Y-C. King, C. Kuo, T-J. King, C. Hu, “Sub-5nm Multiple-Thickness Gate Oxide Technology Using Oxygen Implantation,” International Electron Devices Meeting Technical Digest, pp. 585-588, December 1998.
  645. X. Jin, J-J. Ou, C-H. Chen, W. Liu, M.J. Deen, P.R. Gray, C. Hu, “An Effective Gate Resistance Model for CMOS RF and Noise Modeling,” International Electron Devices Meeting Technical Digest, pp. 961-964, December 1998.
  646. S.S.K. Iyer, X. Lu, N.W. Cheung, C. Hu, “SOI MOSFET on Low Cost SPIMOX Substrate,” International Electron Devices Meeting Technical Digest, pp. 1001-1004, December 1998.
  647. D. Hisamoto, W-C. Lee, J. Kedzierski, E. Anderson, H. Takeuchi, K. Asano, T-J. King, J. Bokor, C. Hu, “A Folded-Channel MOSFET for Deep-Sub-Tenth Micron Era,” International Electron Devices Meeting Technical Digest, pp. 1032-1037, December 1998.
  648. N. Lindert, T. Sugii, S. Tang, C. Hu, “Dynamic Threshold Pass-Transistor Logic for Improved Delay at Lower Power Supply Voltages,” IEEE Journal of Solid-State Circuits, Vol. 34, No. 1, pp. 85-89, January 1999.
  649. W-C. Lee, T-J. King, C. Hu, “Observation of Reduced Boron Penetration and Gate Depletion for Poly-Si0.8Ge0.2 Gated PMOS Devices,” IEEE Electron Device Letters, Vol. 20, No. 1, pp. 9-11, January 1999.
  650. S. Yamamichi, A. Yamamichi, D. Park, T-J. King, C. Hu, “Impact of Time Dependent Dielectric Breakdown and Stress-Induced Leakage Current on the Reliability of High Dielectric Constant (Ba, Sr)TiO3 Thin-Film Capacitors for Gbit-Scale DRAM’s,” IEEE Transactions on Electron Devices, Vol. 46, No. 2, pp. 342-347, February 1999.
  651. J.F. Chen, J. Tao, P. Fang, C. Hu, “Performance and Reliability Comparison Between Asymmetric and Symmetric LDD Devices and Logic Gates,” IEEE Journal of Solid-State Circuits, Vol. 34, No. 3, pp. 367-371, March 1999.
  652. K. Banerjee, G. Wu, M. Igeta, A. Amerasekera, A. Majumdar, C. Hu, “Investigation of Self-Heating Phenomenon in Small Geometry Vias Using Scanning Joule Expansion Microscopy,” IEEE International Reliability Physics Symposium Proceedings, pp. 297-302, March 1999.
  653. J.J. Ou, X. Jin, P.R. Gray, C. Hu, “Recent Developments in BSIM for CMOS RF ac and Noise Modeling,” AACD Workshop ’99, March 1999.
  654. C. Hu, Q. Lu, “A Unified Gate Oxide Breakdown Reliability Model,” 37th IEEE International Reliability Physics Symposium Proceedings, San Diego, CA, pp. 47-51, April 1999.
  655. W-C. Lee, B. Watson, T-J. King, C. Hu, “Enhancement of PMOS Device Performance with Poly-SiGe Gate,” IEEE Electron Device Letters, Vol. 20, No. 5, pp. 232-234, May 1999.
  656. W-D. Liu, X. Jin, Y-C. King, C. Hu, “An Efficient and Accurate Compact Model for Thin-Oxide-MOSFET Intrinsic Capacitance Considering the Finite Charge Layer Thickness,” IEEE Transactions on Electron Devices, Vol. 46, No. 5, pp. 1070-1072, May 1999.
  657. Invited Paper, D. Park, C. Hu, “The Prospect of Process-Induced Charging Damage in Future Thin Gate Oxides,” Microelectronics Reliability, Vol. 39, No. 5, pp. 567-577, May 1999.
  658. W-C. Lee, T-J. King, C. Hu, “Evidence of Hole Direct Tunneling Through Ultrathin Gate Oxide Using P+ Poly-SiGe Gate,” IEEE Electron Device Letters, Vol. 20, No. 6, pp. 268-270, June 1999.
  659. K. Banerjee, A. Mehrotra, A. Sangiovanni-Vincentelli, C. Hu, “On Thermal Effects in Deep Sub-Micron VLSI Interconnects,” Proc. 36th Design Automation Conference, New Orleans, pp. 885-891, June 1999.
  660. W-C. Lee, T-J. King, C. Hu, “Performance Enhancement in Deep-submicron Poly-SiGe-gated CMOS Devices,” 1999 International Symposium on VLSI Technology, Systems, and Applications, Taipei, Taiwan, ROC, pp. 14-18, June 1999.
  661. D. Sylvester, O.S. Nakagawa, C. Hu, “Modeling the Impact of Back-End Process Variation on Circuit Performance,” 1999 International Symposium on VLSI Technology, Systems, and Applications, Taipei, Taiwan, ROC, pp. 58-61, June 1999.
  662. M. Orshansky, C. Spanos, C. Hu, “Circuit Performance Variability Decomposition,” 1999 4th International Workshop on Statistical  Metrology, Kyoto, Japan, pp. 10-13, June 1999.
  663. Award Lecture, ?Transistors of the 21st Century,? W.Y. Pang Foundation Research Excellence Award Lecture, Hsinchu, Taiwan, June 7, 1999.
  664. K. Mayaram, C. Hu, D.O. Pederson, “Oscillations During Inductive Turn-Off in Rectifiers,” Solid-State Electronics 43, pp. 677-681, June 1999.
  665. C. Hu, “Silicon Nanoelectronics for the 21st Century,” Nanotechnology, pp. 113-116, June 1999.
  666. K. Yang, Y-C. King, C. Hu, “Quantum Effect in Oxide Thickness Determination From Capacitance Measurement,” 1999 Symposium on VLSI Technology, Kyoto, Japan, pp. 77-78, June 14-16, 1999.
  667. J.J. Ou, X. Jin, C. Hu, P.R. Gray, “Submicron CMOS Thermal Noise Modeling from an RF Perspective,” 1999 Symposium on VLSI Technology, Kyoto, Japan, pp. 151-152, June 14-16, 1999.
  668. V. Subramanian, J. Kedzierski, N. Lindert, H. Tam, Y. Su, J. McHale, K. Cao, T.J. King, J. Bokor, C. Hu, “A Bulk-Si-Compatible Ultrathin-Body SOI Technology for Sub-100 nm MOSFETs,” 1999 57th Annual Device Research Conference Digest, pp. 28-29, June 1999.
  669. K.J. Yang, C. Hu, “MOS Capacitance Measurements for High-Leakage Thin Dielectrics,” IEEE Transaction on Electron Devices, Vol.46, No. 7, pp. 1500-1501, July 1999.
  670. K. Ishimaru, J.F. Chen, C. Hu, “Channel Width Dependence of Hot-Carrier Induced Degradation in Shallow Trench Isolated PMOSFET’s,” IEEE Transaction on Electron Devices, Vol.46, No. 7, pp. 1532-1536, July 1999.
  671. Y-C. King, T-J. King, C. Hu, “A Long-Refresh Dynamic/Quasi-Nonvolatile Memory Device with 2-nm Tunneling Oxide,” IEEE Electron Device Letters, Vol. 20, No. 8, pp. 409-411, August 1999.
  672. Invited Paper, S. Kamohara, Y. Okuyama, Y. Manabe, K. Okuyama, K. Kubota, D. Park, C. Hu, “Quantitative analysis of SILCs (stress-induced leakage currents) based on the inelastic trap-assisted tunneling model, “SPIE Conference on Microelectronic Device Technology III,  Santa Clara, CA, Vol. 3881, pp. 206-214, September 1999.
  673. W. Liu, C. Hu, “BSIM3v3 MOSFET Model,” International Journal of High Speed Electronics and Systems,” Vol. 9, No. 3, pp. 671-701, September 1999.
  674. P. Su, S.K.H. Fung, F. Assaderaghi, C. Hu, “A Body-Contact SOI MOSFET Model for Circuit Simulation,” 1999 IEEE International SOI Conference Proceedings, Rohnert Park, CA, pp. 50-51, October 1999.
  675. M. Orshansky, J.C. Chen, C. Hu, “Direct Sampling Methodology for Statistical Analysis of Scaled CMOS Technologies,” IEEE Transactions on Semiconductor Manufacturing,” Vol. 12, No. 4, pp. 403-408, November 1999.
  676. L. Chang, C. Kuo, C. Hu, A. Kalnitsky, A. Bergemont, P. Francis, “A CMOS-Compatible Single-Poly Cell for Use as a Non-Volatile Memory,” International Semiconductor Device Research Symposium, Charlottesville, VA, pp.57-50, December 1-3, 1999.
  677. Y-C. Yeo, V. Subramanian, J. Kedzierski, P. Xuan, T-J. King, J. Bokor, C. Hu, “Nanoscale SiGe-Channel Ultra-Thin-Body Silicon-on-Insulator P-MOSFETs,” International Semiconductor Device Research Symposium, Charlottesville, VA, pp. 295-297, December 1-3, 1999.
  678. Q. Lu, Y-C. Yeo, K. Yang, R. Lin, T.-J. King, C. Hu, S.C. Song, H.F. Luan, D-L. Kwong, X. Guo, X. Wang, T-P. Ma, “Comparison of 14Å TOX, EQ JVD and RTCVD Silicon Nitride Gate Dielectrics for Sub-100 nm MOSFETs,” International Semiconductor Device Research Symposium, Charlottesville, VA, pp.489-492, December 1-3, 1999.
  679. X. Huang, W-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y-K. Choi, K. Asano, V. Subramanian, T-J. King, J. Bokor,  C. Hu, “Sub 50-nm FinFET: PMOS,” IEDM Technical Digest, Washington, DC, pp. 67-70, December 5-8, 1999.
  680. K.M. Cao, W. Liu, X. Jin, K. Vasanth, K. Green, J. Krick, T. Vrotsos, C. Hu, “Modeling of Pocket Implanted MOSFETs for Anomalous Analog Behavior,” IEDM Technical Digest, Washington, DC, pp. 171-174, December 5-8, 1999.
  681. W. Jin, S.K.H. Fung, W. Liu, P.C.H. Chan, C. Hu, “Self-Heating Characterization for SOI MOSFET Based on AC Output Conductance,” IEDM Technical Digest, Washington, DC, pp. 175-178, December 5-8, 1999.
  682. M.S. Krishnan, L. Chang, T-J. King, J. Bokor, C. Hu, “MOSFETs with 9 to 13 A Thick Gate Oxides,” IEDM Technical Digest, Washington, DC, pp. 241-244, December 5-8, 1999.
  683. M. Orshansky, L. Milor, L. Nguyen, G. Hill, Y. Peng, C. Hu, “Intra-Field Gate CD Variability and Its Impact On Circuit Performance,” IEDM Technical Digest, Washington, DC, pp. 479-482, December 5-8, 1999.
  684. T. Sato, D. Sylvester, Y. Cao, C. Hu, “Accurate In-situ Measurement of Noise Peak and Delay Induced by Interconnect Coupling,” 2000 IEEE International Solid-State Circuit Conference, TP13.7, San Franciso, CA, pp. 226-227, February 7-9,  2000.
  685. Y-C. Yeo, V. Subramanian, J. Kedzierski, P. Xuan, T-J. King, J. Bokor, C. Hu, “Nanoscale Ultra-Thin-Body Silicon-on-Insulator P-MOSFET with a SiGe/Si Heterostructure Channel,” IEEE Electron Device Letters, Vol. 21, No. 4, pp. 161-163, April 2000.
  686. I. Polishchuk, C. Hu, “Polycrystalline Silicon/Metal Stacked Gate for Threshold Voltage Control in Metal-Oxide-Semiconductor Field-Effect Transistors,” Applied Physics Letters, Vol. 76, No. 14, pp. 1938-1940, April 2000.
  687. K. Banerjee, D. Y. Kim, A. Amerasekera, C. Hu, S. S. Wong, and K. E. Goodson, “Microanalysis of VLSI Interconnect Failure Modes under Short-Pulse Stress Conditions,” IEEE Annual International Reliability Physics Symposium Proceedings (IRPS),  pp. 283-288, April 10-13, 2000.
  688. S.F.Tin, A.A. Osman, K. Mayaram, C. Hu, “A Simple Subcircuit Extension of the BSIM3v3 Model for CMOS RF Design,” IEEE Journal of Solid-State Circuits, pp. 612-624, April 2000.
  689. M. Igeta, K. Banerjee, G. Wu, C. Hu, A. Majumdar, “Thermal Characteristics of Submicron Vias Studied by Scanning Joule Expansion Microscopy,” IEEE Electron Device Letters, Vol. 21, No. 5, pp. 224-226, May 2000.
  690. Y-K. Choi, K. Asano, N. Lindert, V. Subramanian, T-J. King, J. Bokor, C. Hu, “Ultrathin-Body SOI MOSFET for Deep-Sub-Tenth Micron Era,” IEEE Electron Device Letters, Vol. 21, No. 5, pp. 254-255, May 2000.
  691. Y. Cao, T. Sato, M. Orshansky, D. Sylvester, C. Hu, “New Paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Simulation,” Custom Integrated Circuits Conference (CICC), 2000, Proceedings of the IEEE 2000, pp. 201-204, May 2000.
  692. P. Su, S.K.H. Fung, S. Tang, F. Assaderaghi, C. Hu, “BSIMPD: A Partial-Depletion SOI MOSFET Model for Deep-Submicron CMOS Designs,” Custom Integrated Circuits Conference (CICC), 2000, Proceedings of the IEEE 2000, pp. 197-200, May 2000.
  693. Invited Presentation, C. Hu, “CMOS Device Scaling,” Proceedings 2000 Design Automation Conference, p. 85, June 5-9, 2000.      
  694. Q. Lu, Y-C. Yeo, P. Ranade, H. Takeuchi, T-J. King, C. Hu, S.C. Song, H.F. Luan, D-L. Kwong, “Dual-Metal Gate Technology for Deep-Submicron CMOS Transistors,” 2000 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, pp. 72-73, June 13-15, 2000.
  695. X. Jin, K. Cao, J-J. Ou, W. Liu, Y. Cheng, M. Matloubian, C. Hu, “An Accurate Non-Quasistatic MOSFET Model for Simulation of RF and High Speed Circuits,” 2000 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, pp. 196-197, June 13-15, 2000.
  696. W-C. Lee, C. Hu, “Modeling Gate and Substrate Currents due to Conduction- and Valence-Band Electron and Hole Tunneling,” 2000 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, pp. 198-199, June 13-15, 2000.
  697. Y-K. Choi, Y-C. Jeon, P. Ranade, H. Takeuchi, T-J. King, J. Bokor, C. Hu, “30nm Ultra-Thin-Body SOI MOSFET with Selectively Deposited Ge raised S/D,” 58th Device Research Conference Digest, Denver, CO, pp. 23-24, June 19-21, 2000.
  698. Y-C. Yeo, Q. Lu, W-C. Lee, T-J. King, C. Hu, “Scaling Limit of Silicon Nitride Gate Dielectric for Future CMOS Technologies,” 58th Device Research Conference, Denver, CO, p. 65, June 19-21, 2000.
  699. P. Xuan, J. Kedzierski, V. Subramanian, J. Bokor, T-J. King, C. Hu, “60nm Planarized Ultra-Thin Body Solid Phase Epitaxy MOSFETs,” 58th Device Research Conference, Denver, CO, pp. 67-68, June 19-21, 2000.
  700. T. Sato, Y. Cao, D. Sylvester, C. Hu, “Characterization of Interconnect Coupling Noise Using In-situ Delay-Change Curve Measurements,” 2000 IEEE ASIC/SOC Conference, FA..8.1, Washington, DC, pp. 321-325, September 13-16, 2000.
  701. Keynote Speaker, C. Hu, “Alternative CMOS Device Structures and Technologies,” Intel Process Technology Conference 2000, Portland, OR, October 7, 2000.
  702. Y-C. Yeo, Q. Lu, W-C. Lee, T-J. King, C. Hu, X. Wang, X. Guo, T.P. Ma, “Direct Tunneling Gate Leakage Current in Transistors with Ultrathin Silicon Nitride Gate Dielectric,” IEEE Electron Device Letters, Vol. 21, No. 11, pp. 540-542, November 2000.
  703. D. Hisamoto, W-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T-J. King, J. Bokor, C. Hu, “FinFET–A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, Vol. 47, No. 12, pp. 2320-2325, December 2000.
  704. J. Kedzierski, P. Xuan, E.H. Anderson, J. Bokor, T-J. King, C. Hu, “Complementary Silicide Source/Drain Thin-Body MOSFETs for the 20nm Gate Length Regime,” IEDM Meeting 2000, IEDM Technical Digest, San Francisco, CA, pp. 57-60, December 10-13, 2000.
  705. Q. Lu, R. Lin, P. Ranade, Y-C. Yeo, X. Meng, H. Takeuchi, T-J. King, C. Hu, H. Luan, S. Lee, W. Bai, C-H. Lee, D-L. Kwong, X. Guo, X. Wang, T-P. Ma, “Molybdenum Metal Gate MOS Technology for Post-SiO2 Gate Dielectrics,” IEDM Meeting 2000, IEDM Technical Digest, San Francisco, CA, pp. 641-644, December 10-13, 2000.
  706. L. Chang, S. Tang, T-J. King, J. Bokor, C. Hu, “Gate Length Scaling and Threshold Voltage Control of Double-Gate MOSFETs,” IEDM Meeting 2000, IEDM Technical Digest, San Francisco, CA, pp. 719-722, December 10-13, 2000.
  707. X. Huang, Y. Cao, D. Sylvester, S. Lin, T-J. King, C. Hu, “RLC Signal Integrity Analysis of High-Speed Global Interconnects,” IEDM Meeting 2000, IEDM Technical Digest, San Francisco, CA, pp. 731-734, December 10-13, 2000.
  708. Y-C. Yeo, Q. Lu, T-J. King, C. Hu, T. Kawashima, M. Oishi, S. Mashiro, J. Sakai, “Enhanced Performance in Sub-100 nm CMOSFETs using Strained Epitaxial Silicon-Germanium,” IEDM Meeting 2000, IEDM Technical Digest, San Francisco, CA, pp. 753-756, December 10-13, 2000.
  709. K. M. Cao, W.-C. Lee, W. Liu, X. Jin, P. Su, S. K. Fung, J. X. An, B. Yu, C. Hu, “BSIM4 Gate Leakage Model Including Source-Drain Partition,” IEDM Meeting 2000, IEDM Technical Digest, San Francisco, CA, pp. 815-818, December 10-13, 2000.
  710. Y. Cao, X. Huang, D. Sylvester, N. Chang, C. Hu, “A New Analytical Delay and Noise Model for On-Chip RLC Interconnect,” IEDM Meeting 2000, IEDM Technical Digest, San Francisco, CA, pp. 823-826, December 10-13, 2000.
  711. K. Saino, S. Horiba, S. Uchiyama, Y. Takaishi, M. Takenaka, T. Uchida, Y. Takada, K. Koyama, H. Miyake, C. Hu, “Impact of Gate-Induced Drain Leakage Current on the Tail Distribution of DRAM Data Retention Time,” IEDM Meeting 2000, IEDM Technical Digest, San Francisco, CA, pp. 837-840, December 10-13, 2000.
  712. M. Orshansky, J. An, C. Jiang, B. Liu, C. Riccobene, C. Hu, “Efficient Generation of Pre-Silicon MOS Model Parameters for Early Circuit Design,” IEEE Journal of Solid-State Circuits, Vol. 36, No. 1, pp. 156-159, January 2001.
  713. Invited Review, C. Hu, “Scaling CMOS Devices Through Alternative Structures,” Science in China (Series F), Vol. 44, No. 1, pp. 1-7, February 2001.
  714. S. Tang, L. Chang, N. Lindert, Y.-K. Choi, W.-C. Lee, X. Huang, V. Subramanian, J. Bokor, T.-J. King, C. Hu, “FinFET – A Quasi-Planar Double-Gate MOSFET,” ISSCC 2001 Digest of Technical Papers, p. 118-119, February 2001.
  715. I. Polishchuk, Q. Lu, Y.-C. Yeo, T.-J. King, C. Hu, “Intrinsic Reliability Projections for a Thin JVD Silicon Nitride Gate Dielectric in P-MOSFET,” IEEE Transactions on Device and Materials Reliability, Vol. 1, No. 1, pp. 4-8, March 2001.
  716. Y.-C. King, T.-J. King, C. Hu, “Charge-Trap Memory Device Fabricated by Oxidation of SixGe1-x,” IEEE Transactions on Electron Devices, Vol. 48, No. 4, pp. 696-700, April 2001.
  717. W. Jin, W. Liu, S. K. H. Fung, P. C. H. Chan, C. Hu, “SOI Thermal Impedance Extraction Methodology and Its Significance for Circuit Simulation,” IEEE Transactions on Electron Devices, Vol. 48, No. 4, pp. 730-736, April 2001.
  718. W. Jin, W. Liu, C. Hai, P. C. H. Chan, C. Hu, “Noise Modeling and Characterization for 1.5-V 1.8-GHz SOI Low-Noise Amplifier,” IEEE Transactions on Electron Devices, Vol. 48, No. 4, pp. 803-809, April 2001.
  719. Y.-C. Yeo, Q. Lu, P. Ranade, H. Takeuchi, K. J. Yang, I. Polishchuk, T.-J. King, C. Hu, S. C. Song, H. F. Luan, D.-L. Kwong, “Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric,” IEEE Electron Device Letters, Vol. 22, No. 5, pp. 227-229, May 2001.
  720. X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, C. Hu, “Sub-50 nm P-channel FinFET,” IEEE Transactions on Electron Devices, Vol. 48, No. 5, pp. 880-886, May 2001.
  721. H. Nakayama, P. Su, C. Hu, H. Nakamura, H. Komatsu, K. Takeshita, Y. Komatsu, “Methodology of self-heating free parameter extraction and circuit simulation for SOI CMOS,”  IEEE Conference on Custom Integrated Circuits, pp. 381 – 384, May 2001.
  722. K. Asano, Y.-K. Choi, T.-J. King, C. Hu, “Patterning Sub-30-nm MOSFET Gate with I-Line Lithography,” IEEE Transactions on Electron Devices, Vol. 48, No. 5, pp. 1004-1008, May 2001.
  723. D. Sylvester, C. Hu, “Analytical modeling and characterization of deep-submicrometer interconnect,” Proceedings of the IEEE, Vol. 89, No. 5 , pp. 634-664, May 2001.
  724. Y.-C. King, C. Kuo, T.-J. King, C. Hu, “Optimization of Sub-5-nm Multiple-Thickness Gate Oxide Formed by Oxygen Implantation,” IEEE Transactions on Electron Devices, Vol. 48, No. 6, pp. 1279-1281, June 2001.
  725. Y.-K. Choi, D. Ha, T.-J. King, C. Hu, “Ultra-Thin Body PMOSFETs with Selectively Deposited Ge Source/Drain,” 2001 Symposium on VLSI Technology, Kyoto, Japan, pp. 19-20, June 12-14, 2001.
  726. Q. Lu, R. Lin, P. Ranade, T.-J. King, C. Hu, “Metal Gate Work Function Adjustment for Future CMOS Technology,” 2001 Symposium on VLSI Technology, Kyoto, Japan, pp. 45-46, June 12-14, 2001.
  727. Y.-C. Yeo, P. Ranade, Q. Lu, R. Lin, T.-J. King, C. Hu, “Effects of High-k Dielectrics on the Workfunctions of Metal and Silicon Gates,” 2001 Symposium on VLSI Technology,  Kyoto, Japan, pp. 49-50, June 12-14, 2001.
  728. I. Polishchuk, C. Hu, “Electron Wavefunction Penetration into Gate Dielectric and Interface Scattering – An Alternative to Surface Roughness Scattering Model,” 2001 Symposium on VLSI Technology, Kyoto, Japan, pp. 51-52, June 12-14, 2001.
  729. Invited Paper, C. Hu, “BSIM Model for Circuit Design Using Advanced Technologies,” 2001 Symposium on VLSI Circuits,  Kyoto, Japan, pp. 5-6, June 14-16, 2001.
  730. Plenary Paper, C. Hu, “SOI and nanoscale MOSFETs,” 59th Device Research Conference, Conference Digest, Notre Dame, IN, pp. 3-4, June 25-27, 2001.
  731. I. Polishchuk, T.-J. King, C. Hu, “Physical Origin of SILC and Noisy Breakdown in Very Thin Silicon Nitride Gate Dielectric,” 59th Device Research Conference Technical Digest, Notre Dame, ID, pp. 20-21, June 25-27, 2001.
  732. N. Lindert, Y-K Choi, L. Chang, E. Anderson, W. Lee, T-J. King, J. Bokor, C. Hu, “Quasi-planar NMOSFinFETs with sub-100 nm gate lengths,” 59th Device Research Conference Technical Digest, Notre Dame, ID, pp. 26-27, June 25-27, 2001.
  733. Y.-K. Choi, D. Ha, T.-J. King, C. Hu, “Threshold Voltage Shift by Quantum Confinement in Ultra-thin Body Device,” 59th Device Research Conference Technical Digest, Notre Dame, ID, pp. 85-86, June 25-27, 2001.
  734. M. She, Y-C. King, T-J. King, C. Hu, “Modeling and Design Study of Nanocrystal Memory Devices,”  59th Device Research Conference Technical Digest, Notre Dame, ID, pp. 139-140, June 25-27, 2001.
  735. W.-C. Lee, C. Hu, ” Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction-and valence-band electron tunneling ,” IEEE Transactions on Electron Devices, Vol. 48, No. 7, pp. 1366-1373, July 2001.
  736. Q. Lu, Y.-C. Yeo, K. J. Yang, R. Lin, I. Polishchuk, T.-J. King, C. Hu, S. C. Song, H. F. Luan, D.-L. Kwong, X. Guo, Z. Luo, X. Wang, T.-P. Ma, “Two Silicon Nitride Technologies for Post-Si02 MOSFET Gate Dielectric,” IEEE Electron Device Letters, Vol. 22, No. 7, pp. 324-326, July 2001.
  737. C. Kuo, J. Shinn, T.-J. King, C. Hu, “The Effect of Oxide Traps on FLASH Memory Programming,” IEEE NVSMW, Monterey, CA, August 12-15, 2001.
  738. I. Polishchuk, P. Ranade, T.-J. King, C. Hu, “Dual Work Function Metal Gate CMOS Technology Using Metal Interdiffusion,” IEEE Electron Device Letters, Vol. 22, No. 9, pp. 444-446, September 2001.
  739. Y.-K. Choi, D. Ha, T.-J. King, C. Hu, “Nanoscaleultrathin body PMOSFETs with raised selective germanium source/drain,” IEEE Electron Device Letters, Vol. 22, No. 9, pp. 447-448, September 2001.
  740. I. Polishchuk, Y.-C. Yeo, Q. Lu, T.-J. King, C. Hu, “Hot-Carrier Reliability Comparison for pMOSFETs With Ultrathin Silicon-Nitride and Silicon-Oxide Gate Dielectrics,” IEEE Transactions on Device and Materials Reliability, Vol. 1, No. 3 pp. 158-162, September 2001.
  741. Y. Cao, X. Huang, N. Chang, S. Lin, S. Nakagawa, W. Xie, and C. Hu, ?Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion,? Proceedings of International Symposium on Quality Electronic Design, pp. 185-190, September 2001.
  742. Invited Review, Y.-C. Yeo, Q. Lu, and C. Hu, “MOSFET Gate Oxide Reliability: Anode Hole Injection Model and its Applications,” International Journal High Speed Electronics and Systems, Vol. 11, No. 3, pp. 849-886, 2001.
  743. N. Lindert, L. Chang, Y.-K. Choi, E. H. Anderson, W.-C. Lee, T.-J. King, J. Bokor, C. Hu, “Sub-60-nm quasi-planar FinFETs fabricated using a simplified process,” IEEE Electron Device Letters, Vol. 22, No. 10, pp. 487-489, October 2001.
  744. T. Sato, D. Sylvester, Y. Cao, C. Hu, “Accurate In Situ Measurement of Peak Noise and Delay Change Induced by Interconnect Coupling,” IEEE Journal of Solid-State Circuits, Vol. 36, No. 10, pp. 1587-1591, October 2001.
  745. P. Su, K. Goto, T. Sugii, C. Hu, “Self-Heating Enhanced Impact Ionization in SOI MOSFETs,” IEEE 2001 International SOI Conference, Durango, CA, October 2-4, 2001.
  746. K. Goto, P. Su, Y. Tagawa, T. Sugii, C. Hu, “80nm SOI CMOS Parameter Extraction for BSIMPD,” IEEE 2001 International SOI Conference, Durango, CA, October 2-4, 2001.
  747. X. Xi, K. Cao, X. Jin, H. Wan, M. Chan, C. Hu, “Distortion Simulation of 90nm nMOSFET for RF Applications,” 2001 6th International Conference on Solid-State and Integrated Circuit Technology Proceedings,” Shanghai, China, pp. 247-250, October 22-25, 2001.
  748. P. Ranade, H. Takeuchi, T.-J. King, C. Hu, “Work Function Engineering of Molybdenum Gate Electrodes by Nitrogen Implantation,” Electrochemical and Solid-State Letters, Vol. 4, No. 11, pp. G85-G87, November 2001.
  749. L. Chang, K. J. Yang, Y.-C. Yeo, Y.-K. Choi, T.-J. King, and C. Hu, “Reduction of Direct-Tunneling Gate Leakage Current in Double-Gate and Ultra-thin Body MOSFETs,” IEEE International Electron Device Meeting Technical Digest, pp.99-102, Washington, DC, December 2001.
  750. Y.-K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.-J. King, J. Bokor, C. Hu, “Sub-20 nm CMOS FinFET technologies,” IEEE International Electron Device Meeting Technical Digest, pp. 421-424, December 2001.
  751. Q. Lu, R.   Lin, H.  Takeuchi, T-J. King, C. Hu, K.  Onishi, “Deep-submicron CMOS process integration of HfO 2 gate dielectric with poly-Si gate,” Proceedings of International Semiconductor Device Research Symposium, pp. 377-380, December 2001.
  752. Y.-K. Choi, T.-J. King, C. Hu, “Spacer FinFET: Nano-scale CMOS technology for the terabit era,” Proceedings of International Semiconductor Device Research Symposium, pp. 543-546, December 2001.
  753. I. Polishchuk, P. Ranade, T.-J. King, C. Hu, “Dual work function metal gate CMOS transistors fabricated by Ni-Ti interdiffusion,” International Semiconductor Device Research Symposium, Washington, DC, December 2001.
  754. Y.-K. Choi, T.-J. King, C. Hu, “Nanoscale CMOS spacer FinFET for the terabit era,” IEEE Electron Device Letters, Vol. 23, No. 1, pp. 25-27, January 2002.
  755. R. Lin, Q. Lu, P. Ranade, T.-J. King, C. Hu, “An adjustable work function technology using Mo gate for CMOS devices,” IEEE Electron Device Letters, Vol. 23, No. 1, pp. 49-51, January 2002.
  756. K. Agarwal, Y. Cao, T. Sato, D. Sylvester, and C. Hu, ” Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis, “
     Proceedings of Asia and South Pacific Design Automation Conference, pp. 77-84, January 2002.
  757. M. She, T.-J. King, C. Hu, W. Zhu, Z. Luo, J.-P. Han, T.-P. Ma, “JVD Silicon Nitride as Tunnel Dielectric in p-Channel Flash Memory,” IEEE Electron Device Letters, Vol. 23, No. 2, pp. 91-93, February 2002.
  758. Rappaport Award (best paper of 2002 published in all Electron Device Society journals), Y.-C. Yeo, V. Subramanian, J. Kedzierski, P. Xuan, T.-J. King, J. Bokor, C. Hu, “Design and fabrication of 50-nm thin-body p-MOSFETs with a SiGe heterostructure channel,” IEEE Transactions on Electron Devices, Vol. 49, No. 2, pp. 279-286, February 2002.
  759. Y.-K. Choi, T.-J. King, C. Hu, “Spacer patterning technology for nanoscale CMOS,” IEEE Transactions on Electron Devices, Vol. 49, No. 3, pp. 436-441, March 2002.
  760. P. Su, S. Fung, W. Liu, C. Hu, “Studying the Impact of Gate Tunneling on Dynamic Behaviors of Partially-Depleted SOI CMOS Using BSIMPD,” IEEE 2002 International Symposium on Quality Electronic Design, San Jose, CA, March 18-20, 2002.
  761. I. Polishchuk, P. Ranade, T.-J. King, C. Hu, “Dual work function metal gate CMOS transistors by Ni-Ti interdiffusion,” IEEE Electron Device Letters, Vol. 23, No. 4, pp. 200-202, April 2002.
  762. P. Su, K. Goto, T. Sugii, C. Hu, “Excess hot-carrier currents in SOI MOSFETs and its implications,” IEEE 2002 International Reliability Physics Symposium, Dallas, TX, April 8-11, 2002.
  763. Q. Lu, H.Takeuchi, R.Lin, T-K.King, C. Hu, K. Onishi,  R. Choi, C-S Kang, J-C Lee, “Hot carrier reliability of n-MOSFET with ultra-thin HfO/sub 2/gate dielectric and poly-Si gate, ” Reliability Physics Symposium Proceedings, pp.429-430, April 2002.
  764. Invited Paper, M. Chan, C. Hu, “Engineering BSIM for the Nano-Technology Era and Beyond,” Technical Proceedings of the 5th International Conference on Modeling and Simulation of Microsystems,” San Juan, Puerto Rico, pp. 662-665, April 21-25, 2002.
  765. S. Fung, P. Su, C. Hu, “Present Status and Future Direction of BSIM SOI Model for High-Performance/Low-Power/RF Application,” Technical Proceedings of the 5th International Conference on Modeling and Simulation of Microsystems,” San Juan, Puerto Rico, April 21-25, 2002.
  766. J. He, Y. Wang, X. Zhang, X. Xi, M. Chan, R. Huang, C. Hu, “A Simple Method for Optimization of 6H-SiC Punch-Through Junctions Used in Both Unipolar and Bipolar Power Devices,” IEEE Transactions on Electron Devices, Vol. 49, No. 5, pp. 933-937, May 2002.
  767. P. Su, K. Goto, T. Sugii, C. Hu, “Enhanced substrate current in SOI MOSFETs,” IEEE Electron Device Letters, Vol. 23, No. 5, pp. 282-284, May 2002.
  768. M. Orshansky, L. Milnor, P. Chen, K. Keutzer, C. Hu, “Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 5, pp. 544-553, May 2002.
  769. Y.-C. Yeo, P. Ranade, T.-J. King, C. Hu, Effects of High-k Gate Dielectic Materials on Metal and Silicon Gate Workfundtions,” IEEE Electron Device Letters, Vol. 23, No. 6, pp. 342-344, June 2002.
  770. C. Kuo, T.-J. King, C. Hu, “A capacitorless double-gate DRAM cell, ” IEEE Electron Device Letters, Vol. 23, No. 6, pp. 345-347, June 2002.
  771. FL Yang, HY Chen, FC Chen, YL Chan, KN Yang, CJ Chen, HJ Tao, YK Choi, MS Liang, C Hu, “35 nm CMOS FinFETs, ” Digest of Technical Papers. 2002 Symposium on VLSI Technology, pp.104-105, June, 2002.
  772. J. He, X. Xi, M. Chan, C. Hu, Y. Li, Z. Xing, R. Huang, “Linearly graded doping drift region: a novel lateral voltage-sustaining layer used for improvement or RESURF LDMOS Transistor Performances,” Semiconductor Science and Technology, Vol. 17, No. 6, pp. 721-728, June 2002.
  773. Y. Cao, R. A. Groves, N. D. Zamdmer, J. Plouchart, R. A. Wachnik, X. Huang, T. King, and C. Hu, “Frequency-Independent Equivalent Circuit Model for On-chip Spiral Inductors,” Proceedings of Custom Integrated Circuits Conference, pp. 217-220, June 2002.
  774. Q. Lu, H.Takeuchi, X. Meng, T-J.King, C.Hu, K.Onishi, H.Cho, J.Lee, “Improved performance of ultra-thin HfO/sub 2/CMOSFETs using poly-SiGe gate, “ 2002 Symposium on VLSI Technology, 2002. Digest of Technical Papers, pp. 86- 87, June 2002.
  775. Invited Paper, M. Chan, X. Xi, J. He, C. Hu, “Approaches and options for modeling sub-0.1/spl mu/m CMOS devices,” 2002 IEEE Hong Kong Electron Devices Meeting Proceedings, Hong Kong, pp. 79-82, June 22, 2002.
  776. X. Xi, K. Cao, J. He, H. Wan, M. Chan, C. Hu, “Symmetry realization of BSIM model with dynamic reference method for circuit simulation,” 60th Device Research Conference Technical Digest, Santa Barbara, CA, pp. 65-66, June 24-26, 2002.
  777. I. Polishchuk, K. J. Yang, T.-J. King, C. Hu, “Improved MOSFET electron mobility model for advanced gate dielectric stacks,” 60th Device Research Conference Technical Digest, Santa Barbara, CA, pp. 75-76, June 2002.
  778. I. Polishchuk, Y.-C. Yeo, T.-J. King, C. Hu, “Tunneling through multi-layer gate dielectrics-an analytical model,” 60th Device Research Conference Technical Digest, Santa Barbara, CA, pp. 105-106, June 24-26, 2002.
  779. J. He, X. Xi, M. Chan, C. Hu, Y. Li, X. Zhang, R. Huang, Y. Wang, “Equivalent junction method to predict 3-D effect of curved-abrupt p-n junctions,” IEEE Transactions on Electron Devices, Vol. 49, No. 7, pp. 1322-1325, July 2002.
  780. J. He, X. Xi, M. Chan, K. Cao, C. Hu, Y. Li, X. Zhang, R. Huang, Y. Wang, “Normalized mutual integral difference method to extract threshold voltage of MOSFETs,” IEEE Electron Device Letters, Vol. 23, No. 7, pp. 428-430, July 2002.
  781. J. He, X. Xi, M. Chan, C. Hu, Y. Li, Z. Xing. R. Huang, “Linearly graded doping drift region: a novel lateral voltage-sustaining layer used for improvement of RESURF LDMOS transistor performances,” Semiconductor Science and Technology. Vol. 17, Number 7, July 2002.
  782. YC Yeo, TJ King, C. Hu, “Direct tunneling leakage current and scalability of alternative gate dielectrics, ” Applied Physics Letters, vol. 81, no. 11, pp. 2091-2093, Sept. 2002.
  783. X. Huang, Y. Cao, D. Sylvester, T.-J. King, C. Hu, “Analytical performance models for RLC interconnects and application to clock optimization,” IEEE International ASIC-SoC Conference, Rochester, NY, September 2002.
  784. P. Su, K. Goto, T. Sugii, C. Hu, “A thermal activation view of low voltage impact ionization in MOSFETs,” IEEE Electron Device Letters, Vol. 23, No. 9, pp. 550-552, September 2002.
  785. H. Wan, SKH Fung, P Su, M Chan, C. Hu, “Tendency for full depletion due to gate tunneling current, ” IEEE International SOI Conference, pp.140-142, Oct 2002.
  786. Banquet Speech, C. Hu, “The Role of Silicon Foundry in the SOC Era,” 3rd IEEE Pacific-Rim Conference on Multimedia, Hsinchu, Taiwan, p. 10, December 16-18, 2002.
  787. Plenary Paper, C. Hu, “Nano Semiconductor Technology,” International Electron Devices and Materials Symposium, Taipei, Taiwan, p. 1, December 20-21, 2002.
  788. L. Chang, K. J. Yang, Y.-C. Yeo, I. Polishchuk, T.-J. King, C. Hu, “Direct-tunneling gate leakage current in double-gate and ultrathin body MOSFETs,” IEEE Transactions on Electron Devices, Vol. 49, No. 12, pp. 2288-2295, December 2002.
  789. B. Yu, L. Chang , C Ho, Q Xiang, TJ King, J Bokor, C Hu, MR Lin, ” FinFET scaling to 10 nm gate length ” IEDM Tech. Dig, p. 251-254, Dec. 2002.
  790. FL Yang, HY Chen, FC Chen, CC Huang, CY Chang, HK Chiu, CC Lee, CC Chen, HT Huang, CJ Chen, HJ Tao, YC Yeo, MS Liang, C. Hu, ” 25 nm CMOS Omega FETs, ” IEDM Tech. Dig, p. 255-258, Dec. 2002.
  791. C. Kuo, T-J King, C. Hu, ” A capacitorless double-gate DRAM cell design for high density applications,” IEDM Tech. Dig, p. 243-247, Dec. 2002.
  792. K. J. Yang, T.-J. King, C. Hu, S. Levy, and H. N. Al-Shareef, “Electron Mobility in MOSFETs with Ultrathin RTCVD Silicon Nitride/Oxynitride Stacked Gate Dielectrics,” Solid-State Electronics, Vol. 47, No. 1, pp. 149-153, January 2003.
  793. L Chang, Y-K Choi, J Kedzierski, N Lindert, P Xuan, J Bokor, C. Hu , T-K King, ” Moore’s law lives on,” IEEE Circuits and Devices Magazine, Volume: 19,  Issue: 1, pp.35-42, Jan 2003.
  794. P. Su, S. K. H. Fung, P. W. Wyatt, H. Wan, A. M. Niknejad, M. Chan, C. Hu, “On the body-source built-in potential lowering of SOI MOSFETs,” IEEE Electron Device Letters, Vol. 24, No. 2, pp. 90-92, February 2003.
  795. Y. Cao, C. Hu, X. Huang, A. B. Kahng, I. L. Markov, M. Oliver, D. Stroobandt, D. Sylvester, “Improved A Priori Interconnect Predictions and Technology Extrapolation in the GTX System,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 11, No. 1, pp. 3-14, February 2003.
  796. J. He, X. Xi, M. Chan, A. Niknejad, C. Hu, “Surface-Potential-Plus: An Advanced MOSFET Model,” Sixth International Conference on Modeling and Simulation of Microsystems, San Francisco, CA, Vol.2, pp.262-265, February, 2003.
  797. Invited Paper, M. Chan, Y.Taur, C.H.Lin, J. He, A. Niknejad, C. Hu, “A Framework for Generic Physics Based Double-Gate MOSFET Modeling,” Sixth International Conference on Modeling and Simulation of Microsystems, San Francisco, CA, Vol.2, pp.270-273, February, 2003.
  798. Invited Paper, A. M. Niknejad, M. Chan, C. Hu, B. Brodersen, J. Xi, J. He, S. Emami, C. Doan, Y. Cao, P. Su, H. Wan, M. Dunga, C-H Lin, “Compact Modeling for RF and Microwave Integrated Circuits,” 6th international Conference on Modeling and Simulation of Microsystems, pp. 294-297,San Francisco , USA , Feb. 2003.
  799. J. He, X. Xi, M. Chan, K. Cao, A. Niknejad, C. Hu, “A Physics-Based Analytical Surface Potential and Capacitance Model of MOSFET’s Operation from Accumulation to Depletion Region,” Sixth International Conference on Modeling and Simulation of Microsystems, San Francisco, CA, Vol.2, pp.302-305, February, 2003.
  800. Y. Cao, R. A. Groves, X. Huang, N. D. Zamdmer, J.-O. Plouchart, R. A. Wachnik, T.-J. King, C. Hu, “Frequency-Independent Equivalent-Circuit Model for On-Chip Spiral Inductors,” IEEE Journal of Solid-State Circuits, Vol. 38, No. 3, March 2003.
  801. X. Huang, P. Restle, T. Bucelot, Y. Cao, T.-J. King, C. Hu, “Loop-Based Interconnect Modeling and Optimization Approach for Multigigahertz Clock Network Design,” IEEE Journal of Solid-State Circuits, Vol. 38, No. 3, March 2003.
  802. M. Chan, X. Xi, J He, KM Cao, MV Dunga, AM Niknejad, PK Ko, C Hu, “Practical compact modeling approaches and options for sub-0.1 um CMOS technologies,” Microelectronics Reliability 43 pp. 399-404, 2003.
  803. Y.-C. Yeo, T.-J. King, C. Hu, “MOSFET Gate Leakage Modeling and Selection Guide for Alternative Gate Dielectrics Based on Leakage Considerations,” IEEE Transactions on Electron Devices, Vol. 50, No. 4, pp. 1027-1035, April 2003.
  804. S. Lam, H. Wan, P. Su, P.W. Wyatt, C. L. Chen, A. M. Niknejad, C. Hu, P.K. Ko,M.Chan, “RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology,”  IEEE ELECTRON DEVICE LETTERS, VOL. 24, NO. 4, pp. 251-253, APRIL 2003.
  805. T. Sato, Y. Cao, K. Agarwal, D. Sylvester, C. Hu, “Bidirectional Closed-Form Transformation Between On-Chip Coupling Noise Waveforms and Interconnect Delay-Chang Curves,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 5, pp. 560-572, May 2003.
  806. J. He, Y. Wang, X. Zhang, X. Xi, M. Chan, R.Huang, C.Hu, “A simple method for optimization of 6H-SiC punch-through junctions used in both unipolar and bipolar power devices,” IEEE Transactions on Electron Devices, Volume: 49,  Issue: 5, pp. 933-937, May 2002.
  807. H-Y Chen, C-C Huang, C-Y Chang, Y-C Yeo, F-L Yang, C. Hu, “Scaling of CMOS FinFETs towards 10 nm,” VLSI Technology Symposium, Digest of Technical Papers, pp.46-48,  June 2003.
  808. F-L Yang, H-Y Chen, C-C Huang, C-H Ge, K-W Su, C-C Huang, C-Y Chang, D-W Lin,… M-S Liang, J-Y Sun, C Hu, ” Strained FIP-SOI (finFET/FD/PD-SOI) for sub-65 nm CMOS scaling,”  VLSI Technology Symposium, Digest of Technical Papers, pp.137-138,  June 2003.
  809. C. Kuo, T.-J. King, C. Hu, “Direct Tunneling RAM (DT-RAM) for High-Density Memory Applications,” IEEE Electron Device Letters, Vol. 24, No. 7, pp. 475-477, July 2003.
  810. Y Cao, M Orshansky, T. Sato, D. Sylvester, C.Hu,” Spice up your MOSFET modelling,” IEEE Circuits and Devices Magazine, Volume: 19,  Issue: 4, pp. 17-23, July 2003.  
  811. K-W Su, Y-M Sheu, C-K Lin, S-J Yang, W-J Liang, X. Xi, C-S Chiang, J-K Her, Y-Ti Chia, CH Diaz, C Hu, ” A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical Characteristics,” Proc. of the IEEE Custom Integrated Circuits Conference, pp. 245-248, Sept. 2003. 
  812. Pin Su   Fung, S.K.H.   Wyatt, P.W.   Hui Wan   Mansun Chan   Niknejad, A.M.   Chenming Hu , “A unified model for partial-depletion and full-depletion SOI circuit designs: using BSIMPD as a foundation,” Proc. of the IEEE Custom Integrated Circuits Conference, pp. 241-244, Sept. 2003.
  813. Invited Paper,  L. Chang, Y-K. Choi, D. Ha, P. Ranadw, S. Xiong, J. Bokor, C. Hu, T-J. King ,”Extremely Scaled Silicon Nano-CMOS Devices,” Proceedings of the IEEE, 91, pp.1860-1873, Nov. 2003.
  814. CH Ge, CC Lin, CH Ko, CC Huang, YC Huang, BW Chan, BC Perng, CC Sheu, PY Tsai, LG Yao, CL Wu, TL Lee, CJ Chen, CT Wang, SC Lin, YC  Yeo, C. Hu, ” Process-strained Si (PSS) CMOS technology featuring 3D strain engineering,” IEEE International Electron Devices Meeting ( IEDM) Technical Digest, pp.73-76, Dec. 2003.
  815. H Wang, YP Wang, SJ Chen, CH Ge, SM Ting, JY Kung, RL Hwang, HK Chiu, LC Sheu, PY Tsai, LG Yao, SC Chen, HJ Tao, YC Yeo, WC Lee, C.   Hu, ” Substrate-strained silicon technology: process integration, ” IEEE International Electron Devices Meeting ( IEDM) Technical Digest, pp.61-64, Dec. 2003.
  816. F-L Yang, C-C Huang, H-Y Chen, J-J Liaw, T-X Chung, H-W Chen, C-Y Chang, C-C Huang, K-H Chen, D-H Lee……. C. Hu, “A 65nm node strained SOI technology with slim spacer,” IEEE International Electron Devices Meeting ( IEDM) Technical Digest, pp.627-630, Dec. 2003.
  817. C-H. Lin, P. Su, Y. Taur, X. Xi, J. He, A. M. Niknejad, M. Chan, and C. Hu, “Circuit Performance of Double-Gate SOI CMOS,” International Semiconductor Device Research Symposium (ISDRS), pp. 148-149, Washington D.C. , Dec. 2003.
  818. C-H Lin,  J. He, X. Xi, H. Kam, A. M. Niknejad, M. Chan, and C. Hu, “The Impact of Scaling on Volume Inversion in Symmetric Double-Gate MOSFETs,” International Semiconductor Device Research Symposium (ISDRS), pp. 226-227, Washington D.C., Dec. 2003.
  819. Invited Paper, M. Chan, X. Xi, J. He, C-H. Lin, T.-Y. Man, M. Dunga, B. Heydari, H. Wan, A. M. Niknejad, and C. Hu, “The Next Generation BSIM Model Extending from Conventional to Double-Gate MOSFETs”, The 1st International Workshop on Compact Modeling (IWCM’04), January 27, 2004, pp. 8-13, Yokohama, Japan.
  820. C. Kuo, T.-J. King, C. Hu, “Bias polarity dependent effects of P+ floating gate EEPROMs,” IEEE Transactions on Electron Devices, Vol. 51, No. 2, pp. 282-285, February 2004.
  821. Best Paper of the Year Award, M. Orshansky, L. Milor, C. Hu, “Characterization of Spatial Intrafield Gate CD Variability, Its Impact on Circuit Performance, and Spatial Mask-Level Correction,” IEEE Transactions on Semiconductor Manufacturing, Vol. 17, No. 1, pp. 2-11, February 2004.
  822. X. Xi, J. He, M. Chan, C-H. Lin, M. Dunga, H. Babak, H. Wan, A.M. Niknejad, C. Hu, “The Development of Next Generation BSIM for Sub-100nm Mixed-Signal Circuit,” NSTI-Nanotech 2004, www.nsti.org, ISBN 0-9728422-8-4 Vol. 2, pp. 51-56, March 2004.
  823. Invited Paper, M. Chan, J. He, X. Xi, C-H Lin, T.Y. Man, X. Lin, P.K. Ko, A.M. Niknejad, C. Hu, “Quasi-2D Compact Modeling for Double-Gate MOSFET,” NSTI-Nanotech 2004, www.nsti.org, ISBN 0-9728422-8-4 Vol. 2, pp. 108-113, March 2004.
  824. J. He, X. Xi, M. Chan, C-H. Lin, A. Niknejad, C. Hu, ” A Non-Charge-Sheet Based Analytical Model of  Undoped Symmetric Double-Gate MOSFETs Using SPP Approach,” IEEE International Symposium on Quality of electronic design, Proc.  International Symposium on Quality of Electronic Design, pp.45-50, April 2004.
  825. Plenary Talk, C. Hu, “Device challenges and opportunities,” VLSI Technology Symposium, p.4-5, June 2004.
  826. F-L Yang, C-C Huang, T-X Chung, H-Y Chen, C-Y Chang, H-W Chen, D-H Lee, S-D Liu, K-H Chen, S. K. Hung, C.H. Diaz, C-M Wu, Y-C See, B.J. Lin, M.S. Liang, Y-C Sun, C, Hu, “45nm node planar-SOI technology with 0.296 /spl mu/m/sup 2/ 6T-SRAM cell,” VLSI Technology Symposium, p.8-9, June 2004.
  827. F-L Yang, D-H Lee, H-Y Chen, C-Y Cheng, S.D. Liu, C-C Huang, T-X Chung, Y-C Yeo, Y. Li, J-W Lee, P. Chen, M-S Liand, C. Hu, “5nm-Gate Nanowire FinFET,” VLSI Technology Symposium, p.196-197, June 2004.
  828. M. Chan, P. Su, H. Wan, C-H. Lin, S. K.-H. Fung, A. M. Niknejad, C. Hu, and P. K. Ko, “Modeling the Floating-Body Effects of Fully Depleted, Partially Depleted and Body-Grounded SOI MOSFETs“, Solid-State Electronics, Vol. 48, No. 6, pp. 969-978, June 2004.
  829. M. Orshansky, L. Milor, M. Bordsky, G. Hill, C. Hu, “Characterization of spatial CD variability, spatial mask-level correction, and improvement of circuit performance,” Proc. SPIE Optical Microlithography XIII, Vol. 4000, p. 602-611, 2004.
  830. Keynote Address, C. Hu, ” CMOS for One More Century? “,  IEEE Custom Integrated Circuits Conference (CICC), p.1-1,  October 2004.
  831. X. Xi, J. He, M. Dunga, C-H. Lin, B. Heydari, H. Wan, M. Chan, A. Niknejad, C.Hu, “The next generation BSIM for sub-100nm mixed-signal circuit simulation “, Custom Integrated Circuits Conference, p. 13-16,  Oct. 2004.
  832. Keynote Paper, C. Hu, “Future Directions of Silicon Devices,” Proc. of Workshop on Synthesis and System Integration of Mixed Information Technology (SASIMI), pp. 3-4, October 2004.
  833. Invited Paper, X. Xi, J. He, M. Dunga, H. Wan, M. Chan, C-H Lin, B. Heydari, A. M. Niknejad, and C. Hu, “BSIM5 MOSFET model,” 7th International Conference on Solid-State and Integrated-Circuit Technology, Beijing, China, Oct. 2004.
  834. Keynote Talk, C. Hu, “Transistors that extend Moore’s Law,”  MIT Club Semiconductor Entrepreneurship Series , Dec. 2004.
  835. H. C-H Wang, S-J Chen, M-F Wang, P-Y Tsai, C-W Tsai, S.M. Ting, S-C Chen, C.H. Diaz, M-S Liang, C. Hu, “Low power device technology with SiGe channel, HfSiON, and poly-Si gate,” IEEE International Electron Devices Meeting ( IEDM) Technical Digest, pp.161-164, Dec. 2004.
  836. Y. Cao, X. Huang, D. Sylvester, T.-J. King, and C. Hu, “Impact of On-Chip Interconnect Frequency-Dependent R(f)L(f) on Digital and RF Design,” IEEE Transactions on Very Larger Scale Integration (VLSI) Systems, Vol. 13, No. 1, pp. 158-162, January 2005.
  837. Jin He, Jane Xi, Mansun Chan, Hui Wan, Mohan Dunga, Babak Heydari, Ali M. Niknejad, Chenming Hu, “Charge-Based Core and the Model Architecture of BSIM5“, Proceedings of the Sixth International Symposium on Quality of Electronic Design (ISQED’05), pp.96-101, March 2005.
  838. Keynote Speech, C. Hu, “Opportunities in CMOS Technologies”, Proc. of International Meeting for Future Electron Devices, Kyoto, pp. 19-20, April 2005.
  839. Invited Paper, J. Watts, C. McAndrew, C. Enz, C. Galup-Montoro, G. Gildenblat, C. Hu, R. von Langevelde, M. Miura-Mattausch, R. Rios, C-T. Sah, ” Advanced Compact Models for MOSFETs,” NSTI-Nanotech Technical Proceedings of the 2005 Workshop on Compact Modeling, pp. 3-12, May 2005.
  840. H. Wan, P. Su, A.M. Niknejad, C. Hu,” RF Modeling for FDSOI MOSFET and Self Heating Effect on RF Parameter Extraction,” STI-Nanotech Technical Proceedings of the 2005 Workshop on Compact Modeling, May 2005.
  841. J. He, M. Chan, C. Hu, “A Compact Model to Predice QM Levels and Inversion Layer Centroid with Parabolic Well approximation,” NSTI-Nanotech Technical Proceedings of the 2005 Workshop on Compact Modeling, May 2005.
  842. C. Hu, “Tale of Two Models,” NSTI-Nanotech Workshp on Compact Modeling, May 2005.
  843. Best Paper Award, C-H. Lin, X. Xi, J. He, L. Chang, R. Q. Williams, M. B. Ketchen, W. E. Haensch, M. Dunga, S. Balasubramanian, A. M. Niknejad, M. Chan, and C. Hu, “Compact Modeling of FinFETs Featuring Independent-Gate Operation Mode,” 2005 IEEE International Symposium on VLSI Technology, Systems, and Applications, Hsinchu, Taiwan, May 2005.
  844. Invited Paper, A.M. Niknrjad, D. Chinh, S. Emami, D. Mohan, X. Xi, H. Jin, R. Brodersen, C. Hu, “Next generation CMOS compact models for RF and microwave applications,” IEEE Radio Frequency integrated Circuits (RFIC) Symposium, 2005. Digest of Papers , pp141-144, June 2005.
  845. Planery Lecture, ” Thr role of new materials in future CMOS technology,” International Conference on Materials for Advanced Technologies (ICMAT), Singapore, July 3-8, 1005.
  846. C.H. Lin, G. Xu, X. Xi, M. Chan, A. M. Niknejad, and C. Hu, “Corner Effect Model for Compact Modeling of Multi-Gate MOSFETs,” SRC TECHCON. Oct. 2005.
  847. M.V. Dunga, X. Xi, A.M. Niknejad, C. Hu, “A Holistic Model for Mobility Enhancement through Process-Induced Stress,” IEEE Conference on Electron Decive and Solid State Circuits, pp. 43-46, Dec. 2005.
  848. A. Hokazono, S. Balasubramanian, K. Ishimuru, H. Ishiuchi, T-J. King, C. Hu, “ MOSFET design for forward body biasing scheme,” IEEE Electron Device Letters, Vol. 27, pp.387-389, May 2006. 
  849. Invited Paper,  M.V. Dunga, C-H. Lin, X. Xi, S. Chen, D.D. Lu, A.M. Niknejad, C. Hu, “BSIM4 and BSIM Multi-Gate Progress,” NSTI-Nanotech 2006 Workshop on Compact Modeling, May, 2006.
  850. C-H. Lin, K. K. Das, L. Chang, R. Q. Williams, W. E. Haensch, and C. Hu, “VDD Scaling for FinFET Logic and Memory Circuits: the Impact of Process Variations and SRAM Stability,” IEEE International Symposium on VLSI Technology, Systems, and Applications, May, 2006.
  851. M.V. Dunga, X.Xi, A.M. Niknejad, C. Hu, “Dynamic Behavior Model for High-k MOSFETs ,” NSTI- Nanotech 2006 Workshop on Compact Modeling, May, 2006.
  852. Keynote Speech,  C. Hu, “From CMOS to Nanotechnology,” 2006 Advanced Semiconductor Manufacturing Conference (ASMC), Boston, May 2006.
  853. Y. Yasuda, C-H. Lin, T-K. King, and C. Hu, ”Impact of HfSiON Induced Flicker Noise on Scaling of Future Mixed-Signal CMOS,” Symposium on VLSI Technology , Hawaii , USA , June 2006.
  854. T.L. Li, W-L. Ho, H-B. Chen, H.C. Wang, C-Y. Chang, C. Hu, “Novel dual-metal gate technology using Mo-MoSix combination,” IEEE Transactions on Electron devices, Vol.53, No.6, pp.1420-1426, June 2006.
  855. A. Hokazono, A. Balasubramanian, S. Ishimura, K. Ishiuchi, C. Hu, T-J. King Liu, “MOSFET Hot-Carrier Reliability Improvement by Forward-Body Bias,” IEEE Electron Device Letters, Volume 27,  Issue 7,  pp. 605-608, July 2006.
  856. M.V. Dunga, C-H, Hsun, X, Xi, A.M.Niknejad, C. Hu, “Modeling Advanced FET Technology in a Compact Model,” IEEE Transactions on electron devices, Vol. 53, Np.9, pp.1971-1978, Sept. 2006.
  857. Best Student Paper Award, CH Lin, MV Dunga, AM Niknejad, C Hu, “A Compact Quantum-Mechanical Model for Double-Gate MOSFET,” International Conference on Solid-State and Integrated Circuit Technology (2006 ICSICT), pp. 1272-1274, October, 2006.
  858. J. Hu, X Xi, A Niknejad, C Hu,”On gate leakage current partition for MOSFET compact model,” Solid State Electronics, Volume 50, Issue 11-12, pp. 1740-1743, November-December, 2006.
  859. Y. Yasuda, C. Hu,”Effect of Fluorine Incorporation on 1/f Noise of HfSiON FETs for Future Mixed-Signal CMOS, “2006 International Electron Devices Meeting Technical Digest, pp.277-280, December, 2006.
  860. CY Lin, CY Wu, CY Wu, TC Lee, FL Yang, C Hu, TY Tseng,”Effect of Top Electrode Material on Resistive Switching Properties of ZrO2 Film Memory Devices,” IEEE Electron Device Letters, Volume 28, Issue 5, pp. 366-368, May 2007.
  861. Invited Paper, C. Hu, C-H. Lin, M. Dunga, D. Lu, A. Niknejad,”A Versatile Multi-gate MOSFET Compact Model: BSIM-MG ,” NSTI-Nanotech 2007 Workshop on Compact Modeling, Santa Clara, USA, May, 2007.
  862. Best Student Paper Award, M V. Dunga, C-H Lin, D D. Lu,W Xiong, C. R. Cleavelin, P. Patruno, J-R Hwang, F-L Yang, A M. Niknejad, C Hu, “BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design,” Symposium on VLSI Technology, Kyoto, Japan, pp.60-61, June 2007.
  863. C-Y Lin, C-Y Wu, C. Hu, T-Y. Tseng, “Bistable Resistive Switching in Al2O3 Memory Thin Films,” Journal of Electrochemical Society, Volume 154, Issue 9, pp. G189-G192, July 2007.
  864. Invited Paper, C, Hu, M. Dunga, C-H. Lin, A. Niknejad, “Compact Modeling for New transistor Structures,” 2007 SISPAD, Simulation of Semiconductor Processes and Devices, Vol. 12, Ed. T. Grasser, S Selberherr, pp. 285-288, Sept. 2007.
  865. C-Y Lin, C-Y Wu, T-Y. Tseng, C. Hu, “Modified resistive switching behavior of ZrO2 memory films based on the interface layer formed by using Ti top electrode,” Journal Applied Physics,  Vol.102, DIELECTRICS AND FERROELECTRICITY, November., 2007.
  866. K. Fukuda, Y. Shimizu, K. Amemiya, M. Kamoshida, C. Hu, “Random Telegraph Noise in Flash Memories – Model and Technology Scaling,” 2007 International Electron Device Meeting Technical Digest, pp. 169-172, December, 2007.
  867. D.D. Lu, M.V. Dunga, C-H Lin, A.M. Niknejad, C. Hu, “A Multi-Gate MOSFET Compact Model Featuring Independent-Gate Operation,” 2007 International Electron Device Meeting Technical Digest, pp. 565-568, December, 2007.
  868. Keynote Paper, C. Hu,”New CMOS devices and compact modeling,” International Workshop on Physics of Semiconductor Devices (IWPSD), Bombay, India, pp.5-7, Dec. 2007.
  869. Y. Yasuda, T. King Liu, C. Hu, “Flicker-noise impact on Scaling of Mixed-signal CMOS with HfSiON, ” IEEE Transaction on Electron Devices, Volume 55, Number 1, pp.417-422, January, 2008.
  870. C-H. Lin, M.V. Dunga, D. Lu, A.M. Niknejad, C, Hu, “Statistical Compact Modeling of Variations in Nano MOSFETs,” International Symposium on VLSI Technology, Systems and Applications (2008 VLSI-TSA), pp.165-166, April, 2008.
  871. Invited Paper, C. Hu, D. Chou, P. Patel, A. Bowonder, “Green Transistor – A VDD Scaling Path for Future Low Power ICs,” International Symposium on VLSI Technology, Systems and Applications (2008 VLSI-TSA), pp.14-15, April, 2008.
  872. A. Bowonder, P. Patel, K. Jeon, J. Oh, P. Majhi, H-H. Tseng, C. Hu, “Low-voltage Green Transistor Using Utra Shallow Junction and Hetero-Tunneling,” 8th International Workshop on Junction Technology (2008 IWJT), Extended abstracts, pp.93-96, May 2008.
  873. A. Bowonder, P. Patel, K. Jeon, J. Oh, P. Majhi, H-H. Tseng, C. Hu, “Low-voltage Green Transistor Using  Hetero-Tunneling,” IEEE Silicon Nanoelectronics Workshop, pp. 1-2, June 2008.
  874. Invited Paper, C. Hu, “BSIM–Making the First International Standard MOSFET Model,” Science in China Series F: Information Sciences, Volume 51, Number 6, pp. 765-773, June, 2008. 
  875. S. Kamohara, C. Hu, T. Okumura, “Deep-Trap Stress Induced Leakage Current Model for Nominal and Weak Oxides,” Japanese Journal of Applied Physics, Vol. 47, No. 8, 2008, pp. 6208–6213  August, 2008.
  876. J. Park, C. Hu, “Air-spacer Self-Aligned Contact MOSFET for future dense memories,” 2008 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2008), pp.313-316, September, 2008.
  877. Keynote Paper, C. Hu, “Green Transistor as a Solution to the IC Power Crisis,” Proceedings of the 8th IEEE International Conference on Solid-State and Integrated Circuit Technology (2008 ICSICT), pp.17-20, October, 2008.
  878. J. Park, C. Hu, “Air spacer MOSFET technology for 20nm node and beyond,” 9th International Conference on Solid-State and Integrated-Circuit Technology, pp. 53-56, Oct. 2008.
  879. A. Hokazono, A. Balasubramanian, S. Ishimura, K. Ishiuchi, T-J. King Liu, C. Hu,”Forward Body Biasing as a Bulk-Si CMOS Technology Scaling Strategy,” IEEE Transactions on Electron Devices, Vol. 55, Issue 10, pp.2657-2664, Oct. 2008.
  880. J.Park, C.Hu, “An Air-Corridor Interconnect Structure”, VLSI Metal Interconnect Conference (VMIC), p229-234, Oct. 2008.
  881. A. Padilla, C.W. Yeung, C. Shin, C. Hu, T-J. King Liu, “Feedback FET: A novel transistor exhibiting steep switching behavior at low bias voltages,” 2008 International Electron Device Meeting, Dec. 2008.
  882. C-H Lin, M.V. Dunga, D.D. Lu, A.M. Niknejad, C. Hu, “Performance-Aware Corner Model for Design for Manufacturing,” IEEE Transaction on Electron Devices, Vol. 56, Issue 4, pp.595-600, April, 2009.
  883. J. Park, C. Hu, “Gate Last MOSFET with Air Spacer and Self-Aligned Contacts for Dense Memories“, International Symposium on VLSI Technology, Systems, and Applications (VLSI TSA), p105-106, Taiwan, Apr. 2009.
  884. Keynote Speech, C. Hu, “A Green Transistor to Reduce IC Power Consumption by 10X?” INC5, International Nanotechnology Conference, Los Angeles, May 2009.
  885. Plenary Paper, C, Hu, “Reduce IC Power Consumption by >10X with a Green Transistor?” IEEE Device Research Conference, pp. 9-10, June 2009.
  886. S. H. Kim, H. Kam, C. Hu, T-J King Liu,” Germanium-source tunnel field effect transistors with record high ION/IOFF,” Symposium on VLSI Technology, pp.178-179, June 2009.
  887. C.W. Yeung, A. Padilla, T-J. King Liu, C. Hu,” Programming characteristics of the steep turn-on/off feedback FET (FBFET),” Symposium on VLSI Technology, pp.6-177, June 2009. 
  888. Keynote Paper, C. Hu, P. Patel, “Green Transistor: A VDD Scaling Path for Future Low Power ICs,” International Symposiun on Advanced Gate Stack Technology (ISAGST), pp. 4-5, Aug. 2009.
  889. P. Patel, K. Jeon, A. Bowonder, C. Hu, “A Low Voltage Steep Turn-Off Tunnel Transistor Design,” International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp.1-4, Sept. 2009.
  890. D.D. Lu, C-H Lin, S. Yao, W. Xiong, F. Bauer, C.R. Cleavelin, A.M. Niknejad, C. Hu,” Design of FinFET SRAM Cells Using a Statistical Compact Model,” International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 1-4, Sept. 2009.
  891. J. Park, C. Hu, “Air-Spacer MOSFET With Self-Aligned Contact for Future Dense Memories,” IEEE Electron Device Letters, Vol.30, No.12, pp.1368-1370, Dec. 2009.
  892. G-L. Luo, S-C Huang, C-T Chung, D. Heh, C-H Chien, C.-C Cheng,Y-J Lee, W-F Wu, C-C Hsu, M-L Kuo, J-Y Yao, M-N Chang, C-W Liu, C. Hu, C-Y Chang, F-L Yang, “A comprehensive study of Ge1-xSix on Ge for the Ge nMOSFETs with tensile stress, shallow junctions and reduced leakage,” IEEE International Electron Devices Meeting (IEDM), pp.1-3, Dec. 2009.
  893. H-Y. Chen, C-C Chen, F-K Hsueh, J-T Liu, C-Y Shen, C-C Hsu, S-L Shy, B-T Lin, H-T Chuang, C-S Wu, C Hu, C-C H, F-L Yang,”16nm functional 0.039µm2 6T-SRAM cell with nano injection lithography, nanowire channel, and full TiN gate,” IEEE International Electron Devices Meeting (IEDM), pp.1-3, Dec. 2009.
  894. T. H. Morshed, M.V. Dunga, J. Zhang, D.D. Lu, A.M. Niknejad, C. Hu, “Compact modeling of flicker noise variability in small size MOSFETs,” IEEE International Electron Devices Meeting (IEDM), pp.1-3, Dec. 2009.
  895. J. Park, C. Hu, “Vacuum-Sheath Interconnect Structure for Dense Memory“, Electron Letters, Volume 45, Issue 25, pp.1294-1296, December 3, 2009.
  896. S. Yao, T. H. Morshed, D. D. Lu, S. Venugopalan, A. M. Niknejad and C. Hu, “A Global Parameter Extraction Procedure for Multi-gate MOSFETs,” International Conference on Microelectronic Test Structures (ICMTS), pp. 79-82, March 2010.
  897. D.D. Lu, C-H. Lin, A. Niknejad, C. Hu, “Compact Modeling of Variation in FinFET SRAM Cells,” Design & Test of Computers, IEEE , vol.27, no.2, pp. 44-50, Mar./Apr. 2010.
  898. Keynote Paper, C. Hu, “Green Transistor for Future Energy Efficient ICs,” Symposium on Nano Device Technology (SNDT), Hsinchu, Taiwan, pp. 3-4, May 4-5 2010.
  899. K. Jeon, W. Loh, P. Patel, YK Chang, Y. Kang, J.Oh, A. Bowonder, C. Park, C.S.Park, C. Smith, P. Majhi, H-H. Tseng, R. Jammy, T. Liu, C. Hu,”Si tunnel transistors with a novel silicided source and 46mV/dec swing,” VLSI Technology Symposium, pp. 121-122, June 2010.
  900. W-Y. Loh, K. Jeon. CY. Kang, J. Oh, P. Patel, C. Smith, J. Barnett, C.Park, T.-J. King Liu, H-H Tseng, P. Majhi, R. Jammy, C. Hu, “Sub-60nm Si tunnel field effect transistors with Ion >100 µA/µm,” Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European, pp. 162 – 165, Sept. 2010.
  901. Keynote Paper, C. Hu, “Paths to energy efficient ICs,” 2010 IEEE International SOI Conference (SOI), pp.1-2, Oct. 2010.
  902. S.W. Kim, S. Agarwal, Z.A. Jacobson, P. Matheu, C. Hu, T.-J. K. Liu, “Tunnel Field Effect Transistor With raised Germanium Source“, IEEE Electron Device Letters, Vol. 31, pp. 1107-1109, Oct. 2010.
  903. B. Schmid, J. Jia, J. Wolfman, Y. Wang, F. Dhaoui, HC Tseng, SR Kim, KS Lee, P. Liu, KJ Han, C. Hu,” Cycling Induced Degradation of a 65nm FPGA Flash Memory Switch”, IEEE International Integrated Reliability Workshop. Oct 2010.
  904. J. Park, C. Hu, “The Effects of Vacuum Spacer Transistors between High Performance and Low Stand-by Power Devices beyond 16nm“, International Conf. in Semiconductor and Integrated Circuit Technology (ICSICT), Nov. 2010.
  905. Invited Paper, C. Hu, P. Patel, A. Bowonder, K. Jeon; S. H. Kim, W-Y. Loh, C. Y. Kang, J. Oh, P. Majhi, A. Javey, T-J. K. Liu, R. Jammy, “Prospect of tunneling green transistor for 0.1V CMOS“, International Electron Devices Meeting (IEDM), pp. 16.1.1 – 16.1.4, Dec. 2010.
  906. Y-C. Fu, W. Hsu, Y-T. Chen, H-S. Lan, C-H. Lee, H-C. Chang, H-Y. Lee, G-L. Luo, C.W. Liu, C. Hu, F-L. Yang, “High mobility high on/off ratio C-V dispersion-free Ge n-MOSFETs and their strain response“, International Electron Devices Meeting (IEDM), pp. 18.5.1 – 18.5.4, Dec. 2010.
  907. C. H. Ho, C-L. Hsu, C-C. Chen, J-T. Liu, C-S. Wu, C-C. Huang, C. Hu, F-L. Yang, “9nm half-pitch functional resistive memory cell with 1µA programming current using thermally oxidized sub-stoichiometric WOx film“, International Electron Devices Meeting (IEDM), pp. 19.1.1 – 19.1.4, Dec. 2010.
  908. C-H. Shen, J-M. Shieh, H-C. Kuo, J.Y. Huang, W-H. Huang, C-W. Hsu, Y-H. Lin, H-Y. Chiu, H-Y. Jhan, C. Hu, F-L. Yang, “Novel 140°C hybrid thin film solar cell/transistor technology with 9.6% conversion efficiency and 1.1 cm2/V-s electron mobility for low-temperature substrates“, International Electron Devices Meeting (IEDM), pp. 31.1.1 – 31.1.4, Dec. 2010.
  909. A.C. Ford, C. W. Yeung, S. Chuang, H. S. Kim. E. Plis, S. Krishna, C. Hu, A. Javey, “Ultrathin body InAs tunneling field-effect transistor on Si“, Applied Physics Letters, Vol. 98, Issue 1, pp. 113105 – 113105-3, March 2011.
  910. Keynote Presentation, C. Hu, “Semiconductor Technology for Low Power ICs“, China Semiconductor Technology International Conference (CSTIC), March 2011.
  911. V. Sriramkumar, D. Lu, T.H. Morshed, Y. Kawakami, P.M. Lee, A.M. Niknejad, C. Hu,”BSIM-CG: A compact model of cylindrical gate /nanowire MOSFETs for circuit simulations”, Proceedings of VLSI-TSA, April 2011, pp. 124-125.
  912. V. Sriramkumar, D. Lu, A.M. Niknejad, C. Hu,“BSIM-IMG: A Turnkey Compact Model for Back-gated FDSOI MOSFETs”, 5th FDSOI Workshop, Hsinchu, Taiwan, April 2011.
  913. Invited Paper, C. Hu, “New Sub-20nm Transistors–Why and How“, Design Automation Conference (DAC), San Diego, CA., pp.460-463, June 2011.
  914. C.Hu, “FinFET vs. UTB-SOI”, VLSI Technology Symposium Panel Session, Kyoto, Japan, June 2011.
  915. M.A. Karim, Y. Chauhan, D. Lu, V. Sriramkunar, A.M. Niknejad, C. Hu, ”Drain Induced Barrier Lowering (DIBL) Effect on Capacitance of Nano-Scale MOSFETs”; Proceedings of Workshop on Compact Modeling; June 2011.
  916. Invited Paper, Y.S. Chauhan, D. Lu, V. Sriramkumar, A.M. Niknejad, C. Hu “Compact Models for sub-22nm MOSFETs”; Proceedings of Workshop on Compact Modeling, June 2011.
  917. D.D. Lu, M.V. Dunga, C-H Lin, A. M. Niknejad, C. Hu, “A computationally efficient compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates“, Solid-State electronics, Vol. 62, Issue 1, pp.31-39, August 2011.
  918. Keynote Speech, C. Hu, “Intel Uses FinFET at 22nm. What, why, and what else?”, 22nd VLSI Design/CAD Symposium, Yunlin, Taiwan, p. 16, Aug. 2-5, 2011.
  919. S.H. Kim, Z. A. Jacobson, P. Patel, C. Hu, T-J. King Liu,” Tunnel FET-based pass-transistor logic for ultra-low-power applications ,” Device Research Conference (DRC), 2011 69th Annual , 10.1109/DRC.2011.5994452, PP.133-134, Sept. 2011. 
  920. Invited Paper, Q. Chen, X.Zhong, Y. Wu, N.Zhu, W. Huang, D. Lu, C. Hu, B.Y. Nguyen, O. Faynot, “An Exercise of ET/UTBB SOI CMOS Modeling and Simulation with BSIM-IMG,” 2011 International SOI Conference, 10.1109/SOI.2011.6081683 , pp.1-2, October, 2011.
  921. Keynote Speech, C. Hu,”Transistors and compact models for 20nm and Beyond,” 9th IEEE International Conference on ASIC, Xiamen, China, Oct. 25-28, 2011.
  922. H-Y Chen, C-C Chen, F-K Hsueh, J-T Liu, S-L Shy, C-S Wu, C-H Chien, C Hu, C-C Huang, F-L Yang, “A Novel Nanoinjection Lithography (NInL) Technology and Its Application for 16-nm Node Device Fabrication ,” Electron Devices, IEEE Transactions on , Vol, 58 , Issue: 11 , 10.1109/TED.2011.2163938 , pp. 3678 – 3686, Nov. 2011.
  923. A. Sachid, C. Hu,” Denser and More Stable FinFET SRAM using Multiple Fin Heights,” Semiconductor Device Research Symposium (ISDRS), Digital Object Identifier: 10.1109/ISDRS.2011.6135203, pp.1-2, Dec. 2011.
  924. C.-A. Jong, P.-J. Sung, M.-Y. Lee, F.-J. Hou, K. Wu, Y.-H. Su, B.-M. Chen, C.-W. Ho, R.-J.Chung, Y.-J. Lee, W.-F. Wu, C. Hu and F.-L. Yang, ” A Novel Bottom-Up Ag Contact (30nm Diameter and 6.5 Aspect Ratio) Technology by Electroplating for 1Xnm and Beyond Technology“, International Electron Devices Meeting (IEDM), pp. 163-166, Dec. 2011.
  925. A. I. Khan, C. W. Yeung, C. Hu and S. Salahuddin, ” Ferroelectric Negative Capacitance MOSFET: Capacitance Tuning & Antiferroelectric Operation,” International Electron Devices Meeting (IEDM), pp. 255-258, Dec. 2011.
  926. M.-C. Chen, C.-Y. Lin, B.-Y. Chen, C.-H. Lin, G.-W. Huang, C.-C. Huang, C. Ho, T. Wang, C. Hu and F.-L. Yang. ” Silicide Barrier Engineering Induced Random Telegraph Noise in 1Xnm CMOS Contacts,” 2011 International Electron Devices Meeting (IEDM), pp. 626-629, Dec. 2011.
  927. S.-H. Hsu, C.-L. Chu, W.-H. Tu, Y.-C. Fu, P.-J. Sung, H.-C. Chang, Y.-T. Chen, L.-Y. Cho, W. Hsu, G.-L. Luo, C. W. Liu, C. Hu and F.-L. Yang,”Nearly Defect-Free Ge Gate-All-Around FETs on Si Substrates,” International Electron Devices Meeting (IEDM), pp. 825-828, Dec. 2011.
  928. Y.-J. Hsiao, T.-J. Hsueh, J.-M. Shieh, Y.-M. Yeh, C.-C. Wang, B.-T. Dai, W.-W. Hsu, J.-Y. Lin, C.-H. Shen, C. W. Liu, C. Hu and F.-L. Yang, ” Bifacial CIGS (11% Efficiency)/Si Solar Cells by Cd-Free and Sodium-Free Green Process Integrated with CIGS TFTs,” International Electron Devices Meeting (IEDM), pp. 864-867, Dec. 2011.    S. Venugopalana, D D. Lu, Y. Kawakamib, P. M. Lee,     A. M. Niknejada, C. Hu,” BSIM-CG: A compact model of cylindrical/surround gate MOSFET for circuit simulations“, Solid-State Electronics, Volume 67, Issue 1, P.79–89, Jan. 2012.
  929. Keynote Speech, C. Hu, “Beyond the Planar Transistor,” Xilinx Inaugural Emerging Technology Symposium, February, 2012.
  930. Keynote Speech, C. Hu,”3D FinFET-New Structure Rejuvenates the Transistor!” Synopsys User group Meeting, March 25-27, 2012.
  931. Keynote Paper, C. Hu,”Thin-body FinFET as scalable low voltage transistor ,” International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), pp. 1-4, April 2012.
  932. T-C Lien, J-M Shieh,  W-H Huang,  C-H Tu,  C.W. Wang, C-H Shen, C-L Pan, C. Hu, F-L Yang,”Fast programming metal-gate Si quantum dot nonvolatile memory using green nanosecond laser spike annealing ,” Applied Physics Letters, Vol. 100, Issue. 14, pp. 143501 – 143501-4, April 2012.
  933. M. Chen, C-Y Lin, B-Y Chen,  C-H Lin, C-H Ho, T. Wang, C. Hu, F-L Yang, ”  Random Telegraph Noise in 1X-nm CMOS Silicide Contacts and a Method to Extract Trap Density ,” IEEE Electron device Letters, pp. 591 – 593, April 2012.
  934. C-H Shen,  J-MShieh,T-T Wu, J-Y Huang, C-H Huang, B-T Dai, C. Hu, F-L Yang,”CIGS solar cell integrated with high mobility microcrystalline Si TFTs on 30×40 cm2 glass panels for self powered electronics ,” Conference on Lasers and Electro-Optics (CLEO), PP. 1-2, May, 2012.
  935. Keynote Speech, C. Hu,”FinFET and the New Scaling Path to Small Size and Low Power,” IEEE International Systems and Circuits Symposium, Seoul, May 2012.
  936. M-C Chen,  C-H Lin,  C-Y Lin,  F-K. Hsueh,   W.H. Huang,  Y-C Lien, H-C Chen,J-M Shieh,  C-H Ho, C. Hu, F-J Yang, “Sub -fM DNA sensitivity by self-aligned maskless thin-film transistor-based SoC bioelectronics ,” Symposium on VLSI Technology, pp. 127-128, June, 2012.
  937. Keynote Paper, C. Hu, “3D FinFET and other sub-22nm transistors ,” IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, pp. 1-5, July 2012.
  938. A. Sachid, C. Hu, “Denser and More Stable SRAM Using FinFETs With Multiple Fin Heights“, IEEE Trans. on Electron Devices, pp.2037 – 2041, Aug. 2012.
  939. S. Venugopalan, K. Dandu, S. Martin, R. Taylor, C.R. Cirba, X. Zhang, A.M. Niknejad, C. Hu, “A non-iterative physical procedure for RF CMOS compact model extraction using BSIM6“, IEEE Custom Integrated Circuits Conference (CICC), pp.1-4, Sept. 2012.
  940. Y.S. Chauhan,  S. Venugopalan, M. A. Karim, S. Khandelwal, N. Paydavosi, P. Thakur,  A. Niknejad, C. Hu,”BSIM — Industry standard compact MOSFET models ,” Proceedings of the European Solid-State Device Research Conference (ESSDERC), pp.46-49, Sept. 2012.
  941. M A Karim, Y S Chauhan, S. Venugopalan, A B Sachid, D. Lu, BY. Nguyen, O. Faynot, A. Niknejad, C. Hu, “Extraction of Isothermal Condition and Thermal Network in UTBB SOI MOSFETs “, IEEE Electron Device Letters, pp. 1306-1308, Sept. 2012.        
  942. S. Venugopalan, M A Karim, A. Niknejad, C. Hu, D.D. Lu, ” Compact Models for Real Device Effects in FinFETs“, SISPAD, Denver, Sept. 2012.
  943. C. Yeung, A I Khan, J-Y Cheng,  S. Salahuddin and C. Hu, “Non-Hysteretic Negative Capacitance FET with Sub-30mV/dec Swing over 106X Current Range and ION of 0.3mA/μm without Strain Enhancement at 0.3V VDD,” SISPAD, Denver, Sept. 2012.
  944. K. Wu, A. Sachid, F-L Liang, C. Hu, ” Toward 44% Switching Energy Reduction for FinFETs with Vacuum Gate Spacer“, SISPAD Denver, Sept. 2012.
  945. Keynote Paper, C. Hu,”FinFET and UTB–How to Make Very Short Channel MOSFETs,” Electrochemical Society (ECS) Trans. Volume 50, Issue 9, pp. 17-20, 2013, Symposium Oct. 2012.
  946. C-H Ho,H-H Huang, M-T  Lee, C-H Hsu, T-Y Lai, W-C Chiu, M-Y Lee, T-H Chou, Y-D Yao, C. Hu F-L Yang,”Threshold Vacuum Switch (TVS) on 3D-stackable and 4F2 cross-point bipolar and unipolar resistive random access memory ,” International Electron Devices Meeting (IEDM), pp. 2.8.1 – 2.8.4, Dec. 2012.
  947. C-H Shen, J-M Shieh, T-T Wu, U-P Chiou, H-C Kuo, Y-L Chueh,  C-W Liu, C. Hu, F-L-Yang,”Hybrid CIS/Si near-IR sensor and 16% PV energy-harvesting technology ,” International Electron Devices Meeting (IEDM), pp. 12.2.1 – 12.2.4, Dec. 2012.
  948. C-M Lin, H-C Chang, Y-T Chen, I-H Wong, H-S Lan, C-W Liu, C. Hu, F-L Yang,” Interfacial layer-free ZrO2 on Ge with 0.39-nm EOT, κ=43, 2×10−3 A/cm2 gate leakage, SS =85 mV/dec, Ion/Ioff =6×105, and high strain response ,” International Electron Devices Meeting (IEDM), pp. 23.2.1 – 23.1.4, Dec. 2012.
  949. Y.-J. Lee, S.-S. Chuang, C.-I. Liu, F.-K. Hsueh, P.-J. Sung, H.-C. Chen, C.-T. Wu, T.-Y. Tseng, C. Hu,  F.-L. Yang,”Full low temperature microwave processed Ge CMOS achieving diffusion-less junction and Ultrathin 7.5nm Ni mono-germanide ,” International Electron Devices Meeting (IEDM), pp. 23.3.1 – 23.3.4, Dec. 2012.
  950. Y-C Lien, C-M Shieh, W-H Huang, W-S Hsieh, C-H Tu, C. Wang, C-H Shen, C. Hu, F-L yang,”3D Ferroelectric-like NVM/CMOS hybrid chip by sub-400 °C sequential layered integration ,” International Electron Devices Meeting (IEDM), pp. 33.6.1 – 33.6.4, Dec. 2012.
  951. Y. Singh Chauhan, M. A. Karim,S. Venugopalan, H. Agarwal, P. Thakur,N. Paydavosi, A. Niknejad, C Hu, ” BSIM6.0 MOSFET Compact Model“, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, 2013.
  952. C-H Wang,C-LHsu,W-C Chiu, T-Y Lai, C-H Ho, C. Hu, F-L Yang, Y. C. Chou, “High sensitivity DNA sieving technology by entropic trapping in 3D artificial nano-channel matrices ,” International Conference on Micro Electro Mechanical Systems (MEMS), pp. 899-902, Jan. 2013.
  953. J-Y Cheng, C W Yeung, C Hu, “Extraction of Front and Buried Oxide Interface Trap Densities in Fully Depleted Silicon-On-Insulator Metal-Oxide-Semiconductor Field-Effect Transistor“, ECS Solid State Letters, Vol.2, Issue 5, Q32-Q35, Feb. 2013.
  954. Keynote Speech,  C. Hu, “The changing device technology”, ISQED, March 2013.
  955. S. Venugopalan, MA karim, S salahudin, AM Niknejad, C Hu,” Phenomenological Compact Model for QM Charge Centroid in Multigate FETs“, IEEE Transactions on Electron Devices, Vol.60, Issue 4, pp. 1480-1484, April, 2013.
  956. SH Chen, MC Chen, HM Chen, CF Shih, YY Ho, WF Wu, CH Ho, C Hu, FL Yang, “Schottky barrier free NiSi/Si junction technology by Yb-implantation for 1xnm CMOS applications”, International Symposium of VLSI Technology, Systems, and Applications (VLSI-TSA), April 2013.
  957. Keynote Paper, C.Hu, ” From Reliability Research to FinFET”, International Reliability Physics Symposium (IRPS), April, 2013.
  958. “Microchips – Heart of Electronics”, California Commonwealth Club Forum, April 23, 2013.
  959. Best Paper Award, CW Yeung, AI Khan, A Sarker, S. Salahuddin, C Hu, “Low power negative capacitance FETs for future quantum-well body technology“, International Symposium of VLSI Technology, Systems, and Applications (VLSI-TSA), April 2013.
  960. BJ Sheu, C-S Chang, Y-H Chen, K. Wang,C. Hou, J. Sun, C. Hu, “Enabling circuit design using FinFETs through close ecosystem collaboration“,  International Symposium of VLSI Technology, Systems, and Applications (VLSI-TSA), April 2013.
  961. S-H Chen, M-C Chen, H-M Chen, C-F Shih, CH Ho, C Hu, F-L Yang, “Schottky barrier free NiSi/Si junction technology by Yb-implantation for 1xnm CMOS applications“, International Symposium of VLSI Technology, Systems, and Applications (VLSI-TSA), pp. 1-2, April 2013.
  962. Y-T Chen, H-C Chang, I-S Wong, C-M Lin, H-C Sun, H-J Ciou, W-T Yeh, S-J Lo, CW Liu, C Hu, F-L Yang, ” EUV degradation of high performance Ge MOSFETs”, International Symposium of VLSI Technology, Systems, and Applications (VLSI-TSA), April 2013.
  963. Keynote Speech, C. Hu, “FinFET is a Beginning”, mentor graphics U2U Symposium, April 25, 2013.
  964. C-M Lin, H-C Chang, I-H Wong, S-J Luo, CW Liu, C Hu,” Interfacial layer reduction and high permittivity tetragonal ZrO2 on germanium reaching ultrathin 0.39 nm equivalent oxide thickness“,  Applied Physics Letters, Vol.102, Issue 23, 232906 – 232906-3, June 2013.
  965. M-C Cheng, C-H Lin, Y-F Hou, CH Ho ; T. Wang ; A.B. Sachid, C. Hu, F-L. Yang, ” A 10 nm Si-based bulk FinFETs 6T SRAM with multiple fin heights technology for 25% better static noise margin“,  Symp. on VLSI Technology (VLSIT), pp. T218 – T219, June 2012.
  966. Y.Singh Chauhan, S. Venugopalan, N. Paydavosi, P. Kushwaha, S. Jandhyala, J.P. Duarte, S. Agnihotri, C. Yadav, H. Agarwal, A. Niknejad, C. Hu, ” BSIM compact MOSFET models for SPICE simulation“, Proceedings of the 20th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES), pp. V, June 2013.
  967. Y. Zeng, C-I. Kuo, R. Kapadia, C-Y. Hsu, A. Javey, C. Hu, ” Two-dimensional to three-dimensional tunneling in InAs/AlSb/GaSb quantum well heterojunctions“,  J. Appl. Phys. Vol.114, No. 2, July, 2013.
  968. I-F. Cheng, H-C. Chang, T-Y Chen, C. Hu, F-L Yang, ” Rapid (<5 min) Identification of Pathogen in Human Blood by Electrokinetic Concentration and Surface-Enhanced Raman Spectroscopy“,  Scientific Reports, Article number: 2365, doi:10.1038/srep02365, Aug. 2013.
  969. J. P. Duarte, N. Paydavosi, S. Venugopalan, A. Sachid, C. Hu, “Unified FinFET Compact Model: Modelling Trapezoidal Triple-Gate FinFETs,” SISPAD, Glasgow, Sept. 2013.
  970. Keynote Paper,  C. Hu, ” Compact Modeling for the Changing TransistorCompact Modeling for the Changing Transistor“, SISPAD, Glasgow, Sept. 2013.
  971. N. Paydavosi, S. Venugopalan, A. Sachid, A. Niknejad, C. Hu, S. Dey, S. Martin, X. Zhang, ” Flicker noise in advanced CMOS technology: Effects of halo implant“, Proceedings of the European Solid-State Device Research Conference (ESSDERC), Page(s): 238 – 241, Sept. 2013.
  972. CW Yeung, A.I. Khan, S. Salahuddin, C. Hu,” Device design considerations for ultra-thin body non-hysteretic negative capacitance FETs“, Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S), October 2013.
  973. Keynote Paper,  C. Hu,” A Bold New Era of Nano Materials and Devices“, IEEE Nanotechnology Materials and Devices Conference (IEEE NMDC 2013), October, 2013.
  974. C-C Yang, S-H Chen, J-M Shieh, W-H Huang, T-Y Hsieh, C-H Shen, T-T Wu, H-H Wang,Y-J Lee, FJ Hou, CL Pan, C Hu, F-L Yang, ” Record-high 121/62 μA/μm on-currents 3D stacked epi-like Si FETs with and without metal back gate“, 2013 IEEE International Electron Devices Meeting (IEDM), Page(s): 29.6.1 – 29.6.4, Dec. 2013.
  975. CH Shen, JM Shieh, TW Wu, WH Huang, CC Yang, HJ Wan, CD Lin, HH Wang, BY Chen, GW Huang, YC Lien, S. Wong, C. Wang, YC Lai, CF Chen, MF Chang, C. Hu, FLYang, ” Monolithic 3D chip integrated with 500ns NVM, 3ps logic circuits and SRAM“, 2013 IEEE International Electron Devices Meeting (IEDM), Page(s): 9.3.1 – 9.3.4, Dec. 2013.
  976. Invited Paper, Y.S. Chauhan, S. Venugopalan, M.-A. Chalkiadaki, M.A.U. Karim, H. Agarwal, S. Khandelwal, N. Paydavosi, J.P. Duarte, C.C. Enz, A.M. Niknejad, C. Hu,” BSIM6: Analog and RF Compact Model for Bulk MOSFET“, IEEE Transactions on Electron Devices, Volume: 61 , Issue: 2, Page(s): 234 – 244, Feb. 2014.
  977. S. Khandelwal, J. Duarte, Sriramkumar V., N. Paydavosi, D. Lu, C-H. Lin, M. Dunga, S. Yao, T. Morshed, A. Niknejad, C. Hu, “BSIM-IMG102.6.0 Independent Multi-Gate MOSFET Compact Model,” Technical Manual, Dept.of EECS, University of California, 2014.
  978. Keynote,  C. Hu,” New Devices and Materials for Energy Efficient Electronics”, KAUST-NSF Conference on Electronic Materials, Devices and Systems for Sustainable Future, Feb. 2014.
  979. Y J Lee, T C Cho, S S Chuang, F K Hsueh, Y L Lu, P L Sung, H C Chen, M I Current, T Y Tseng, S Chao, C Hu, F L Yang,” Low-Temperature Microwave Annealing Processes for Future IC Fabrication—A Review“,  IEEE Transactions on Electron Devices, Volume: 61 , Issue: 3,  Page(s): 651 – 665, March 2014.
  980. H. Agarwal, S. Khandelwal, J. P. Duarte, Y. S. Chauhan, A. Niknejad, C. Hu,”BSIM6.1.0 MOSFET Compact Model”, Technical Manual, Dept.of EECS, University of California, 2014.
  981. A. B. Sachid, H. Fang, A. Javey, C. Hu,” Series resistance and mobility in mechanically-exfoliated layered transition metal dichalcogenide MOSFETs“, Proceedings of Technical Program of 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), April 2014.
  982. A. B. Sachid, S. Khandelwal, C. Hu,” Body-bias effect in SOI FinFET for low-power applications: Gate length dependence “, Proceedings of Technical Program of 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), April 2014.
  983. T. Roy, M. Tosun, J. S. Kang, A. B. Sachid, S. B. Desai, M. Hettick, C. Hu , A. Javey, ” Field-Effect Transistors Built from All Two-Dimensional Material Components“, ACS Nano, 2014, 8 (6), pp 6259–6264, April 2014.
  984. A. B. Sachid, C. Hu,” Impact of channel doping on the device and NBTI performance in FinFETs for low power applications “, Proceedings of Technical Program of 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), April 2014.
  985. C. Yadav, P. Kushwaha, S. Khandelwal, J.P. Duarte, Y.S. Chauhan, C.Hu,” Modeling of GaN-Based Normally-Off FinFET “, IEEE Electron Device Letters, Vol. 35, Issue 6, pp. 612-614, June 2014.
  986. T-E. Hsieh, E.Y. Chang, Y-Z. Song, H-C. Wang, S-C. Liu, S. Salahuddin, C. Hu,”Gate Recessed Quasi-Normally OFF Al2O3/AlGaN/GaN MIS-HEMT With Low Threshold Voltage Hysteresis Using PEALD AlN Interfacial Passivation Layer,” IEEE Electron Device Letters, Volume: 35, Issue:7, pp.732 – 734, July 2014.
  987. S. Khandelwal, JP. Duarte, YS. Chauhan, C. Hu, “ Modeling 20-nm Germanium FinFET With the Industry Standard FinFET Model”, IEEE Electron Device Letters, Volume: 35, Issue: 7, pp. 711 – 713, July 2014.
  988. HL Quang, EY Chang, HD Trinh, YC Lin, HQ Nguyen, YY Wong, HB Do, S Salahuddin, C Hu, ” Electrical Characteristics of n, p-In0.53Ga0.47As MOSCAPs With In Situ PEALD-AlN Interfacial Passivation Layer“, IEEE Transactions on Electron Devices, Volume: 61 , Issue: 8, pp. 2774 – 2778, August 2014.
  989. MC. Chen, CY. Lin, KH Li, LJ Li, CH. Chen, CH Chuang, MD Lee, YJ. Chen, T. Wang, FL. Yang, C. Hu, ”Hybrid Si/TMD 2D electronic double channels fabricated using solid CVD few-layer-MoS2 stacking for Vth matching and CMOS-compatible 3DFETs,” IEEE International Electron Devices Meeting (IEDM), Pages: 33.5.1 – 33.5.4, December 2014.
  990. P/ Kushwha, C. Yadav, H. Agarwal, Y.S. Chauhan, J. Srivatsava, S. Khandelwal, J.P. Duarte, C. Hu,”BSIM-IMG with improved surface potential calculation recipe,” 2014 Annual IEEE  India Conference (INDICON), pp.1 – 4, December 2014
  991. F.M. Fahad, C. Hu, M.M. Hussain,” Simulation Study of a 3-D Device Integrating FinFET and UTBFET,”   IEEE Transactions on Electron Devices, Volume: 62, Issue: 1, pp. 83 – 87, January 2015.
  992. P. Kushwaha, N. Paydavosi, S. Khandelwal, C. Yadav, H. Agarwal, J. P. Duarte, C. Hu, Y. Chauhan,” Modeling the impact of substrate depletion in FDSOI MOSFETs,” Solid-State Electronics, Volume 104, Pages 6–11, February 2015.
  993. H. Agarwal, C. Gupta, P. Kushwaha, J.P. Duarte, S. Khandelwal, C. Hu, Y.S. Chauhan, “Analytical Modeling and Experimental Validation of Threshold Voltage in BSIM6 MOSFET Model,”  IEEE Journal of the Electron Devices Society, Volume: 3, Issue: 3, pp, 240 – 243, March 2015.
  994. H. Agarwal, S. Khandelwal, S. Dey, C. Hu, Y.S. Chauhan, ”Analytical Modeling of Flicker Noise in Halo Implanted MOSFETs,”  IEEE Journal of the Electron Devices Society, Volume: 3, Issue: 4, Pages: 355 – 360, March 2015.
  995. S. Khandelwal, P. Kushwaha, A. Medury, J. Duarte, D. Lu, C-H. Lin, M. Dunga, Sriramkumar V., S. Yao, T. Morshed, N. Paydavosi, S. Jandhyala, Y. S. Chauhan, S. Salahuddin, C. Hu, “BSIM-IMG102.6.0 Independent Multi-Gate MOSFET Compact Model,” Technical Manual, Dept.of EECS, University of California, 2015.
  996. V. Hu, A.B. Sachid, C-T. Lo, P. Su, C. Hu,”Electrostatic integrity and performance enhancement for UTB InGaAs-OI MOSFET with high-k dielectric through spacer design,” Proceedings of Technical Program of 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), April 2015.
  997. Y. Zeng, C-I Kuo, C. Hsu, M. Najmzadeh, A. Sachid, R. Kapadia, C. Yeung, E.Y. Chang, C. Hu, A. Javey, “Quantum Well InAs/AlSb/GaSb Vertical Tunnel FET With HSQ Mechanical Support,” , IEEE Transactions on  Nanotechnology, Volume:14 ,  Issue: 3, 580 – 584, May 2015.
  998. C. Hu, S. Salahuddin, C-I. Lin, A, Khan,”0.2V Adiabatic NC-FinFET with 0.6mA/um Ion and 0.1nA/um Ioff”, Device Research Conference (DRC), pp.39-40, June 2015.
  999. S. Khandelwal, J. P. Duarte, A. Medury, Y. S. Chauhan, C. Hu,” New industry standard FinFET compact model for future technology nodes,” VLSI Technology 2015 Symposium, pp. T62 – T63, June 2015.
  1000. S. Khandelwal, J.P. Duarte, A. Medury, Y.S. Chauhan, S. Salahuddin, C. Hu,” Modeling SiGe FinFETs With Thin Fin and Current-Dependent Source/Drain Resistance,” IEEE Electron Device Letters, Volume: 36, Issue: 7, pp. 636 – 638, July 2015.
  1001. H. Agarwal, S. Khandelwal, S. Dey, C. Hu, Y.S. Chauhan,” Analytical Modeling of Flicker Noise in Halo Implanted MOSFETs,” IEEE Journal of the Electron Devices Society, Volume:3,Issue: 4, pp. 355 – 360, July 2015.
  1002. S. Khandelwal, H. Agarwal, J. Duarte, K. Chan, S. Dey,Y. Chauhan,” Modeling STI Edge Parasitic Current for Accurate Circuit Simulations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume:34, Issue: 8, pp. 1291 – 1294, August 2015.
  1003. K.Yao, S. Khandelwal, F. Sammoura, A. Kazama, C. Hu, L. Lin,” Piezoelectricity-Induced Schottky Barrier Height Variations in AlGaN/GaN High Electron Mobility Transistors,” IEEE Electron Device Letters, Volume:36,  Issue: 9, pp. 902 – 904,  Sept. 2015.
  1004. J.P. Duarte, S. Khandelwal, A. Medury, C. Hu, P. Kushwaha, H. Agarwal, A. Dasgupta, Y. S. Chauhan,” BSIM-CMG: Standard FinFET compact model for advanced circuit design,” European Solid-State Circuits Conference (ESSCIRC), pp. 196 – 201, Sept. 2016.
  1005. C. R. Serrao, A. M. Diamond, S.-.in Hsu, L. You, S. Gadgil, J.Clarkson, C. Carraro, R. Maboudian, C. Hu, S. Salahuddin,” Highly crystalline MoS2 thin films grown by pulsed laser deposition,” Appl. Phys. Lett. 106, 052101, Oct. 2015.
  1006. Keynote Speech,  C. Hu,” What After FinFET?,” IEEE ASICON, November 4-7 2015. 
  1007. Q.H. Luc, H.B. Do, M.H.H. Ha, C. Hu, Y.C. Lin, E. Y. Chang,” Plasma Enhanced Atomic Layer Deposition Passivated HfO2/AlN/In0.53Ga0.47As MOSCAPs With Sub-Nanometer Equivalent Oxide Thickness and Low Interface Trap Density,” IEEE Electron Device Letters, Volume:36,  Issue: 12, pp. 1277 – 1280, Dec. 2015.
  1008. K-S Li, P-G Chen, T-Y Lai, C-H Lin, C-C Cheng, C-C Chen, Y-J Wei, Y-F Hou, M-H Liao, M-H Lee, M-C Chen, J-M Sheih, W-K Yeh, F-L Yang, S. Salahuddin, C. Hu,” Sub-60mV-swing negative-capacitance FinFET without hysteresis,” IEEE International Electron Devices Meeting (IEDM), pp. 22.6.1 – 22.6.4, Dec. 2015.
  1009. M-C Chen, K-S Li, L-J Li, A-Y Lu , M-Y Li, Y-H Chang, C-H Lin, A. B. Sachid, T. Wang, F-L Yang, C. Hu,” TMD FinFET with 4 nm thin body and back gate control for future low power technology,”  IEEE International Electron Devices Meeting (IEDM), pp. 32.2.1 – 32.2.4, December 2015.
  1010. H.B. Do, Q. H. Luc, M. T. H. Ha, C. Hu, Y. C. Lin, E. Y. Chang,” Impact of AlN Interfacial Dipole on Effective Work Function of Ni and Band Alignment of Ni/HfO2/In0.53Ga0.47As Gate-Stack,” IEEE Transactions on Electron Devices,  Volume:62 ,  Issue: 12, 3987 – 3991, Dec. 2015.
  1011. A.I. Khan, K. Chatterjee, J.P. Duarte, Z. Lu, A.S. Sachid, S. Khandelwal, R. Ramesh, C.Hu, S. Salahuddin,” Negative Capacitance in Short-Channel FinFETs Externally Connected to an Epitaxial Ferroelectric Capacitor,” IEEE Electron Device Letters, Volume:37,  Issue: 1, pp. 111 – 114, January, 2016.
  1012. H. Agarwal, P. Kushwaha, S Khandelwal, C. Hu, Y.S. Chauhan,” Analysis and modeling of flicker noise in lateral asymmetric channel MOSFETs,” Solid-State Electronics, Volume 115, Part A, pp. 33–38, January 2016.
  1013. F.A. Fatah, Y-C Lin, R-X Liu, K-C Yang, T-W Lin, H-T Hsu, J-H Yang, Y. Miyamoto, H. Iwai, C.Hu,” A 60-nm-thick enhancement mode In0.65Ga0.35As/InAs/In0.65Ga0.35As high-electron-mobility transistor fabricated using Au/Pt/Ti non-annealed ohmic technology for low-power logic applications,” Japan Society of Applied Physics Applied Physics Express, Volume 9, Number 2, Jan. 2016.
  1014. S. Khandelwal, H. Agarwal, P. Kushwaha, J.P. Duarte, A. Medury, Y.S. Chauhan, S. Salahuddin, C. Hu,” Unified Compact Model Covering Drift-Diffusion to Ballistic Carrier Transport,” IEEE Electron Device Letters, Volume:37,  Issue: 2, pp. 134 – 137, Feb. 2016.
  1015. T. Roy, M. Tosun, M. Hettick, G.H. Ahn, C. Hu, A. Javey,” 2D-2D tunneling field-effect transistors using WSe2/SnSe2 heterostructures,” Appl. Phys. Lett. 108, 083111, Feb. 2016.
  1016. C-Y  Hsu, C.Y. Chang. E. Y. Chang, C. Hu,” Suppressing Non-Uniform Tunneling in InAs/GaSb TFET With Dual-Metal Gate,” IEEE Journal of the Electron Devices Society, Volume:4,  Issue: 2, pp. 60 – 65, Feb. 2016.
  1017. AB. Sachid, M. Tosun, S.B. Desai, C-Y Hsu, D-H lien, S. R. Madhvapathy, Y-Z Chen, M. hettick, J.S.kanf, Y.Zeng, J-H He, E. Y. Chang, Y-L Chueh, A. Javey, C. Hu,” Monolithic 3D CMOS Using Layered Semiconductors,” Advanced Materials, Feb. 2016.
  1018. B.K. Kompala, P. Kushwaha, H. Agarwal, S. Khandelwal, J.P.Duarte, C. Hu, Y.S. Chauhan,” Modeling of nonlinear thermal resistance in FinFETs,” Japan Society of Applied Physics Applied Physics Express Volume 55, Number 4S, March 2016.
  1019. V.P. Hu, C-T Lo, A. B. Sachid, P. Su, C. Hu,” Corner spacer design for performance optimization of multi-gate InGaAs-OI FinFET with gate-to-source/drain underlap,” 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), April 2016.
  1020. Y-K Lin, S. Khandelwal, A.S. Medury, H. Agarwal, H-L Chang, Y.S. Chauhan, C. Hu,” Modeling of Subsurface Leakage Current in Low Vth Short Channel MOSFET at Accumulation Bias,” IEEE Transactions on Electron Devices, Volume:63,  Issue: 5, pp. 1840 – 1845, May 2016.
  1021. C-I Lin, A.I. Khan, S. Salahuddin, C. Hu,” Effects of the Variation of Ferroelectric Properties on Negative Capacitance FET Characteristics,” IEEE Transactions on Electron Devices, Volume:63,  Issue: 5, pp. 2197 – 2199, May 2016.
  1022. A.B. Sachid, M-C Chen, C. Hu,” FinFET with High-κ Spacers for Improved Drive Current,” IEEE Electron Device Letters, Volume:PP ,  Issue: 99, pp. 1, May 2016.
  1023. P. Kushwaha, S. Khandelwal, J.P. Duart, C. Hu, Y.S. Chauhan,” RF Modeling of FDSOI Transistors Using Industry Standard BSIM-IMG Model,” IEEE Transactions on Microwave Theory and Techniques, Volume:64,  Issue: 6, pp. 1745 – 1751, June 2016.    
  1024. P. Kushwaha, H. Agarwal, S. Khandelwal, J.P. Duart, A. Medury, C. Hu, Y.S. Chauhan,” BSIM-IMG: Compact model for RF-SOI MOSFETs,” Device Research Conference (DRC), pp. 287 – 288, June 2016.
  1025. Keynote,  C. Hu,” The roles of 2D semiconductor in future VLSI,” International Symposium on Device and Applications of Two-dimensional Materials, June 29-30, 2016
  1026. Keynote,  C. Hu,” Why FinFET and What Next?,” ShanghaiTech Workshop on Energy-Efficient Computing, June 30-July1, 2016
  1027. K-S Li, B-W Wu, L-J Li, M-Y Li, C-C Cheng, C-L Hsu, C-H Lin, …C.Hu,”U-shape MOSFET with 10 nm channel length and poly-Si source/drain serving as seed for full wafer CVD MoS2 availability”, IEEE Symposium on VLSI Technology, IEEE Symposium on VLSI Technology, 14-16 June
  1028. Luc Q, Cheng S, Chang P, Do H, Chen J, Ha M, Huynh S, Hu C, Lin Y, Chang E.,” Effects of In-Situ Plasma-Enhanced Atomic Layer Deposition Treatment on the Performance of HfO2/In0.53Ga0.47As Metal-Oxide-Semiconductor Field-Effect Transistors”, IEEE Electron Device Letters 1-1, 2016
  1029. Do HB, Luc QH, Ha MTH, Huynh SH, Hu C, Lin YC, Chang EY,”Methods for Extracting Flat Band Voltage in the InGaAs High Mobility Materials”, IEEE Electron Device Letters 37(9):1100-1103, Sep 2016
  1030. Kushwaha P, Krishna K, Agarwal H, Khandelwal S, Duarte J-P, Hu C, Chauhan YS,” Thermal resistance modeling in FDSOI transistors with industry standard model BSIM-IMG”, Microelectronics Journal V 56, pp171-176, Oct 2016
  1031. Desai SB, Madhvapathy SR, Sachid AB, Llinas JP, Wang Q, Ahn GH, Pitner G, Kim MJ, Bokor J, Hu C, Javey A,”MoS2 transistors with 1-nanometer gate lengths”, Science  354(6308), pp99-102, 06 Oct 2016
  1032. Kushwaha P, Dasgupta A, Sahu Y, Khandelwal S, Hu C, Chauhan YS,” Characterization of RF Noise in UTBB FD-SOI MOSFET”, IEEE Journal of the Electron Devices Society 4(6), pp 379-386, Nov 2016
  1033. Do HB, Luc QH, Ha MTH, Huynh SH, Hu C, Lin YC, Chang EY,”Investigation of Multilayer TiNi Alloys as the Gate Metal for nMOS In0.53Ga0.47As”, IEEE Transactions on Electron Devices 63(12), pp4714-4719, Dec 2016
  1034. Pahwa G, Dutta T, Agarwal A, Khandelwal S, Salahuddin S, Hu C, Chauhan YS,” Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part I: Model Description”, IEEE Transactions on Electron Devices 63,pp4981-4985 Dec 2016
  1035. Pahwa G, Dutta T, Agarwal A, Khandelwal S, Salahuddin S, Hu C, Chauhan YS,” Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part II: Model Validation”, IEEE Transactions on Electron Devices 63,pp4986-4992 Dec 2016
  1036. Dasgupta, C. Gupta, A.Dutta… C. Hu, Y.S. Chauhan,” Modeling of Body-Bias Dependence of Overlap Capacitances in Bulk MOSFETs”, 30th International Conference on VLSI Design, 7-11 Jan. 2017
  1037. Sachid AB, Huang Y-M, Chen Y-J, Chen C-C, Lu DD, Chen M-C, Hu C,”FinFET With Encased Air-Gap Spacers for High-Performance and Low-Energy Circuits,” IEEE Electron Device Letters 38, pp16-19, Jan 2017
  1038. Khandelwal S, Duarte JP, Khan AI, Salahuddin S, Hu C,”Impact of Parasitic Capacitance and Ferroelectric Parameters on Negative Capacitance FinFET Characteristics”, IEEE Electron Device Letters 38, pp142-144 Jan 2017
  1039. H. Agarwal, C. Gupta, S. Dey, S. Khandelwal, C.Hu, Y. Chauhan,” Anomalous Transconductance in Long Channel Halo Implanted MOSFETs: Analysis and Modeling”, IEEE Transactions on Electron Devices, V 64 , Feb. 2017, P. 376 – 383
  1040. C. Gupta, H. Agarwal, S. Dey; C. Hu, Y. S. Chauhan,” Analysis and modeling of capacitances in halo-implanted MOSFETs”, IEEE Electron Devices Technology and Manufacturing Conference (EDTM), 28 Feb.-2 March 2017
  1041. C. Gupta, H. Agarwal2, Y. K. Lin, A. Ito, C. Hu, Y.S. Chauhan,” Analysis and modeling of zero-threshold voltage native devices with industry standard BSIM6 model”, Japanese Journal of Applied Physics, V. 56, Number 4S, March 2017.
  1042. G. Karbasian, A. Tan, A. Yadav, E. Martin,… C. Hu, S. Salahuddin,” Ferroelectricity in HfO2 thin films as a function of Zr doping”, International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 24-27 April 2017
  1043. D. D. Lu, A. B. Sachid, Y-M Huang, Y-J Chen…C.Hu,” Stressor design for FinFETs with air-gap spacers”, International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 24-27 April 2017
  1044. A. B. Sachid, M-C Chen, C. Hu,” Bulk FinFET With Low- κ Spacers for Continued Scaling”, IEEE Transactions on Electron Devices, V. 64 , April 2017, pp 1861 – 1864
  1045. H. B. Do, Q. H. Luc, M. H. Ha… C. Hu, Y. C. Lin, E. Y. Chang,” Investigation of Mo/Ti/AlN/HfO2 High-k Metal Gate Stack for Low Power InGaAs ,NMOS Device Application”, IEEE Electron Device Letters, V. 38 , May 2017, pp. 552 – 555
  1046. C. H. Wu, S. C. Liu, C. K. Huang, Y. C. Chiu, P. C. Han, P. C. Chang, C. Hu, H. Iwai, E. Y. Chang,” High Vth enhancement mode GaN power devices with high Idmax using hybrid ferroe,lectric charge trap gate stack”, Symposium on VLSI Technology, 5-8 June 2017
  1047. Y. Sahu, P. Kushwaha, A. Dasgupta, C. Hu, Y. S. Chauhan,” Compact Modeling of Drain Current Thermal Noise in FDSOI MOSFETs Including Back-Bias Effect”, IEEE Transactions on Microwave Theory and Techniques, V. 65 , July 2017, pp 2261 – 2270
  1048. Y. Zeng, C. Hsu, E. Y. Chang, C. Hu,” Impact of Al content on InAs/AlSb/AlxGa1−xSb tunnelling diode”, Journal of Engineering V. 2017, 7 2017, pp 403 – 406
  1049. S. K. Samal, S. Khandelwal, A. I. Khan, S. Salahuddin, C. Hu, S. K. Lim,” Full chip power benefits with negative capacitance FETs”, IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 24-26 July 2017
  1050. G. Karbasian, R. Reis, A.K. Yadav, A. J. Tan, C. Hu, S. Salahuddin,” Stabilization of ferroelectric phase in tungsten capped Hf0.8Zr0.2O2”, Appl. Phys. Lett. 111, 022907, July 2017
  1051. Y-K Lin, J. P. Duarte, P. Kushwaha, H. Agarwal, A. Sachid, S. Salahuddin, C. Hu,” Compact Modeling Source-to-Drain Tunneling in Sub-10-nm GAA FinFET With Industry Standard Model”, IEEE Transactions on Electron Devices, V. 64, Sept. 2017, pp 3576 – 3581
  1052. K. Chatterjee, S. Kim, G. Karbasian, A.J. Tan, A.Yadav, A. I. Khan, C. Hu, S. Salahuddin,” Self-Aligned, Gate Last, FDSOI, Ferroelectric Gate Memory Device With 5.5-nm Hf0.8Zr0.2O2, High Endurance and Breakdown Recovery”, IEEE Electron Device Letters, V 38, Oct. 2017, pp1379 – 1382
  1053. Y-K Lin, P. Kushwaha, H. Agarwal, H-L Chang, J. Duarte, A. B. Sachid, S. Khandelwal, S. Salahuddin, C. Hu,” Modeling of Back-Gate Effects on Gate-Induced Drain Leakage and Gate Currents in UTB SOI MOSFETs,” IEEE Transactions on Electron Devices, V 64, Oct. 2017, pp 3986 – 3999
  1054. A. B. Sachid, S. B. Desai, A. Javey, C. Hu,” High-gain monolithic 3D CMOS inverter using layered semiconductors”, Appl. Phys. Lett. 111, 222101, Nov. 2017
  1055. A. I. Khan1, M. Hoffmann, K. Chatterjee, Z. Lu, R. Xu, C. Serrao, S. Smith, L.W. Martin, C. Hu, R. Ramesh, S. Salahuddin,” Differential voltage amplification from ferroelectric negative capacitance”, Appl. Phys. Lett. NCFET2019, 253501, Dec. 2017
  1056. V. PH Hu, P-C Chiu, A.B. Sachid, C. Hu,” Negative capacitance enables FinFET and FDSOI scaling to 2 nm node”, IEEE International Electron Devices Meeting (IEDM), 2-6 Dec. 2017
  1057. A.B. Sachid, H-Y Lin, C. Hu,” Nanowire FET With Corner Spacer for High-Performance, Energy-Efficient Applications”, IEEE Transactions on Electron Devices, V 64, Dec. 2017, pp 5181 – 5187
  1058. A. J. Tan, A. K. Yadav, K. Chatterjee, D.K. Sangwan Kim, C. Hu, S. Salahuddin,” A Nitrided Interfacial Oxide for Interface State Improvement in Hafnium Zirconium Oxide-Based Ferroelectric Transistor Technology”, IEEE Electron Device Letters,  V 39, Jan. 2018, pp 95 – 98
  1059. D. Kwon, K. Chatterjee, A.J. Tan, A.K. Yadav, H. Zhou, A.B. Sachid, R.D. Reis, C. Hu, S. Salahuddin,” Improved Subthreshold Swing and Short Channel Effect in FDSOI n-Channel Negative Capacitance Field Effect Transistors”, IEEE Electron Device Letters, V 39, Feb. 2018, pp 300 – 303
  1060. Y-K Lin, P. Kushwaha, J.P. Duarte, H-L Chang… M. Harter, M. Harter, J. Watts, Y. S. Chauhan, S. Salahuddin, C. Hu,” New Mobility Model for Accurate Modeling of Transconductance in FDSOI MOSFETs”, IEEE Transactions on Electron Devices, V 65, Feb. 2018, pp 463 – 469
  1061. A, Dasgupta, P. Rastogi, A. Agarwal, C. Hu, Y. Chauhan,” Compact Modeling of Cross-Sectional Scaling in Gate-All-Around FETs: 3-D to 1-D Transition”, IEEE Transactions on Electron Devices, V 65, March 2018, pp 1094 – 1100
  1062. H. Agarwal, P. Kushwaha, J. P. Duarte, Y-K Lin,…S. Salahuddin, C. Hu,” Designing 0.5 V 5-nm HP and 0.23 V 5-nm LP NC-FinFETs With Improved IOFF Sensitivity in Presence of Parasitic Capacitance”, IEEE Transactions on Electron Devices, V 65, March 2018, pp 1211 – 1216
  1063. Q.H. Luc, K.S. Yang, J.W. Lin, C.C. Chang,…C. Hu,” In0.53Ga0.47As FinFET and GAA-FET With Remote-Plasma Treatment”, IEEE Electron Device Letters, V 39, March 2018, pp 339 – 342
  1064. P. Kushwaha, H. Agarwal, C.K. Dabhi, Y-K Lin, J-P Duarte, C. Hu, Y. Chauhan,” A Unified Flicker Noise Model for FDSOI MOSFETs Including Back-bias Effect”, IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), 16-17 March 2018
  1065. A.B. Sachid, C. Hu,” UTBSOI MOSFET with corner spacers for energy-efficient applications”, International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 16-19 April 2018
  1066. H. Agarwal, P. Kushwaha, J.P. Duarte, Y-K Lin, A.B. Sachid, MY Kao, HL Chang, S. Salahuddin, C. Hu,” Engineering Negative Differential Resistance in NCFETs for Analog Applications”, IEEE Transactions on Electron Devices, V 65, May 2018, pp 2033 – 2039
  1067. H. Zhou, D. Kwon, A.B. Sachid, Y. Liao, K. Chatterjee, A.J. Tan, A.K. Yadav, C. Hu, S. Salahuddin,” Negative Capacitance, n-Channel, Si FinFETs: Bi-directional Sub-60 mV/dec, Negative DIBL, Negative Differential Resistance and Improved Short Channel Effect,” IEEE Symposium on VLSI Technology, 18-22 June 2018
  1068. D. Kwon, Y-H Liao, Y-K Lin, J.P. Duarte, K. Chatterjee, A.J. Tan, A.K. Yadav, C. Hu, Z. Krivokapic, S. Salahuddin,” Response Speed of Negative Capacitance FinFETs”, IEEE Symposium on VLSI Technology, 18-22 June 2018
  1069. C.K. Dabhi, A. Dasgupta, P. Kushwaha, H. Agarwal, C. Hu, Y. Chauhan,” Modeling of Induced Gate Thermal Noise Including Back-Bias Effect in FDSOI MOSFET”, IEEE Microwave and Wireless Components Letters, V 28, July 2018, pp 597 – 599
  1070. Harshit Agarwal  ; Pragya Kushwaha, ; Yen-Kai Lin  ; Ming-Yen Kao, Yu-Hung Liao, Juan-Pablo Duarte, Sayeef Salahuddin, Chenming Hu,” NCFET Design Considering Maximum Interface Electric Field”, IEEE Electron Device Letters, V 39, Aug. 2018, pp1254 – 125
  1071. C. Gupta, S. Dey, H. Agarwal, R. Goel, C. Hu, Y. Chauhan,” Analysis and Modeling of Temperature and Bias Dependence of Current Mismatch in Halo-Implanted MOSFETs”, IEEE Transactions on Electron Devices, V 65, Sept. 2018, pp 3608 – 3616
  1072. M-Y Kao, A.B. Sachid, Y-K Lin, Y-H Liao, H. Agarwal,…S. Salahuddin, C. Hu,” Variation Caused by Spatial Distribution of Dielectric and Ferroelectric Grains in a Negative Capacitance Field-Effect Transistor”, IEEE Transactions on Electron Devices, V 65, Oct. 2018, pp 4652 – 4658
  1073. W-X You, P. Su, C. Hu,” Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits Using SPICE Simulation”, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 15-18 Oct. 2018
  1074. JP Duarte, Y-K Lin, Y-H Liao, A Sachid, M-Y Kao, H Agarwal, P Kushwaha, K Chatterjee, D Kwon, H-L Chang, S Salahuddin, C Hu ,” Negative-capacitance FinFETs: Numerical simulation, compact modeling and circuit evaluation “, 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) ,123-128, Sept. 2108
  1075. C-C Yang, T-Y Hsieh, P-T Huang, K-N Chen…. J-M Shieh, C. Hu, M-C Wu, W-K Yeh,” Location-controlled-grain Technique for Monolithic 3D BEOL FinFET Circuits, IEEE International Electron Devices Meeting (IEDM), 1-5 Dec. 2018
  1076. Y-K Lin, M-Y Kao, H. Agarwal, Y-H Liao, P. Kushwaha, K. Chatterjee, J. P. Duarte, H-L Chang, S. Salahuddin, C. Hu, “Effect of Polycrystallinity and Presence of Dielectric Phases on NC-FinFET Variability”, IEEE International Electron Devices Meeting (IEDM), 1-5 Dec. 2018
  1077. K-S Li, Y-J Wei, Y-J Chen, W-C Chiu…. J-M Shieh, W-K Yeh, S. Salahuddin, C. Hu,” Negative-Capacitance FinFET Inverter, Ring Oscillator, SRAM Cell, and Ft”, IEEE International Electron Devices Meeting (IEDM), 1-5 Dec. 2018
  1078. C. Gupta, N. Mohamed, H. Agarwal, R. Goel, C. Hu, Y. Chauhan,”Accurate and Computationally Efficient Modeling of Nonquasi-Static Effects in MOSFETs for Millimeter-Wave Applications  IEEE Transactions on Electron Devices, V 66, 1 Jan. 2019, pp 44-51
  1079. H. Agarwa, P. Kushwaha, Y-K Lin, M-Y Kao, YH Liao, A. Dasgupta, S. Salahuddin, C Hu, “Proposal for Capacitance Matching in Negative Capacitance Field-Effect Transistors’, IEEE Electron Device Letters, V 40, March 2019, pp 463 – 466
  1080. A.K. Yadav, K.X. Nguyen, Z. Hong, P. García-Fernández, P. Aguado-Puente, C.T. Nelson, S. Das, B. Prasad, D. Kwon, S. Cheema, A.I. Khan, C. Hu, J. Íñiguez, J. Junquera, L-Q Chen, D.A. Muller, R Ramesh, S. Salahuddin, “Spatially resolved steady-state negative capacitance”, Nature, V 565, pp 468–471, 2019
  1081. Y-H Chen, C-J Su, C. Hu, T-L Wu, “Effects of Annealing on Ferroelectric Hafnium–Zirconium–Oxide-Based Transistor Technology”, IEEE Electron Device Letters,  V 40, March 2019, pp 467 – 470
  1082. W-X You, P. Su, C. Hu, “Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits”, IEEE Transactions on Electron Devices, V 66, April 2019, pp 2004 – 2009
  1083. Y-K Lin, H. Agarwal, P. Kushwaha, M-Y Kao…S. Salahuddin, C. Hu,” Analysis and Modeling of Inner Fringing Field Effect on Negative Capacitance FinFETs”, IEEE Transactions on Electron Devices, V 66, April 2019, pp 2023 – 2027
  1084. M-Y Kao, Y-K Lin, H. Agarwal, Y-H Liao, P. Kashwahal, A. Dasgupta, S. Salahuddin, C. Hu,” Optimization of NCFET by Matching Dielectric and Ferroelectric Nonuniformly Along the Channel”, IEEE Electron Device Letters, V 40, May 2019, pp 822 – 825
  1085. P. Kushwaha, H. Agarwal, Y-K Lin, A. Dasgupta, M-Y Kao, Y. Lu, Y. Yue, X. Chen, J. Wang, W. Sy, F. Yang, PR. Chidi Chidambaram, S. Salahuddin, C. Hu, “Characterization and Modeling of Flicker Noise in FinFETs at Advanced Technology Node”, IEEE Electron Device Letters, V 40, June 2019, pp 985 – 988
  1086. Y-K Lin, H. Agarwal, M-Y Kao, J. Zhou, Y-H Liao, A. Dasgupta, P. Kushwaha, S. Salahuddin, C. Hu,” Spacer Engineering in Negative Capacitance FinFETs”, IEEE Electron Device Letters, V 40, June 2019, pp 1009 – 1012
  1087. C. Gupta, H. Agarwal, R. Goel, C. Hu, Y. Chauhan,” Improved Modeling of Bulk Charge Effect for BSIM-BULK Model”, IEEE Transactions on Electron Devices,  V 66, June 2019, pp 2850 – 2853
  1088. D. Kwon, S. Cheema, N. Shanker, K. Chatterjee, Y-H Liao, A.J. Tan, C. Hu, S. Salahuddin,” Negative Capacitance FET With 1.8-nm-Thick Zr-Doped HfO2 Oxide”, IEEE Electron Device Letters, V 40, June 2019, pp 993 – 996
  1089. K. Chatterjee et al., “Challenges to Partial Switching of Hf0.8Zr0.2O2 Gated Ferroelectric FET for Multilevel/Analog or Low-Voltage Memory Operation,” in IEEE Electron Device Letters, vol. 40, no. 9, pp. 1423-1426, Sept. 2019
  1090. Y. Liao, D. Kwon, Y. Lin, A. J. Tan, C. Hu and S. Salahuddin, “Anomalously Beneficial Gate-Length Scaling Trend of Negative Capacitance Transistors,” in IEEE Electron Device Letters, vol. 40, no. 11, pp. 1860-1863, Nov. 2019
  1091. H Agarwal, C Gupta, R Goel, P Kushwaha, YK Lin, MY Kao, JP Duarte, C Hu , “BSIM-HV: High-Voltage MOSFET Model Including Quasi-Saturation and Self-Heating Effect“,IEEE Transactions on Electron Devices 66 (10), 4258-4263 ,Dec 2019
  1092. D. Kwon et al., “Near Threshold Capacitance Matching in a Negative Capacitance FET With 1 nm Effective Oxide Thickness Gate Stack,” in IEEE Electron Device Letters, vol. 41, no. 1, pp. 179-182, Jan. 2020
  1093. A. Dasgupta et al., “BSIM Compact Model of Quantum Confinement in Advanced Nanosheet FETs,” in IEEE Transactions on Electron Devices, vol. 67, no. 2, pp. 730-737, Feb. 2020
  1094. A. J. Tan , K. Chatterjee , Ji. Zhou , D. Kwon , YH Liao , Su. Cheema , C. Hu, and S. Salahuddin “Experimental Demonstration of a Ferroelectric HfO2-Based Content Addressable Memory Cell,” in IEEE Electron Device Letters, vol. 41, no. 2, pp. 240-243, Feb. 2020
  1095. W. You, P. Su and C. Hu, “A New 8T Hybrid Nonvolatile SRAM With Ferroelectric FET,” in IEEE Journal of the Electron Devices Society, vol. 8, pp. 171-175, 2020 Feb.
  1096. A. Dasgupta, S. S. Parihar, H. Agarwal, P. Kushwaha, Y. S. Chauhan and C. Hu, “Compact Model for Geometry Dependent Mobility in Nanosheet FETs,” in IEEE Electron Device Letters, vol. 41, no. 3, pp. 313-316, March 2020
  1097. Cheema, S.S., Kwon, D., Shanker, N. et al. “Enhanced ferroelectricity in ultrathin films grown directly on silicon” Nature 580, 478–482 (Apr. 2020).
  1098. Y. Chen, C. Su, T. Yang, C. Hu and T. Wu, “Improved TDDB Reliability and Interface States in 5-nm Hf0.5Zr0.5O2 Ferroelectric Technologies Using NH3 Plasma and Microwave Annealing,” in IEEE Transactions on Electron Devices, vol. 67, no. 4, pp. 1581-1585, April 2020
  1099. A. J. Tan, L. Wang, Y. Liao, J. Bae, C. Hu and S. Salahuddin, “Reliability of Ferroelectric HfO2-based Memories: From MOS Capacitor to FeFET,” 2020 Device Research Conference (DRC), Apr. 2020, pp. 1-2
  1100. H. P. Wong et al., “A Density Metric for Semiconductor Technology [Point of View],” in Proceedings of the IEEE, vol. 108, no. 4, pp. 478-482, April 2020
  1101. V. P. Hu, H. Lin, Y. Lin and C. Hu, “Optimization of Negative-Capacitance Vertical-Tunnel FET (NCVT-FET),” in IEEE Transactions on Electron Devices, vol. 67, no. 6, pp. 2593-2599, June 2020
  1102. A.J. Tan, M. Pešić, L. Larcher, Y-H Liao, L-C Wang, J-H Bae, C. Hu, S. Salahuddin, “Hot Electrons as the Dominant Source of Degradation for Sub-5nm HZO FeFETs”, IEEE Symposium on VLSI Technology, June 2020.
  1103. YJ Lin,CY Teng,SJ Chang,YF Liao,C Hu,CJ Su,YC Tseng “Role of electrode-induced oxygen vacancies in regulating polarization wake-up in ferroelectric capacitors” Applied Surface Science, Volume 528, 30 October 2020
  1104. J-H Bae, D. Kwon, N. Jeon, S. Cheema, A.J. Tan, C. Hu, S. Salahuddin,”Highly Scaled, High Endurance, Ω-Gate, Nanowire Ferroelectric FET Memory Transistors”, IEEE Electron Device Letters, Nov. 2020, p.1637 – 1640.
  1105. Y-HLiao, D. Kwon, S. Cheema, N. Shanker, A. J. Tan, M-Y Kao, L-C Wang, C. Human, S. Salahuddin, “Electric Field-Induced Permittivity Enhancement in Negative-Capacitance FET”, IEEE Trans. Electron Devices, P. 1346, March 2021.
  1106. MY Kao; YH Liao; G Pahwa; A Dasgupta; S Salahuddin; C Hu,”Energy Storage and Reuse in Negative Capacitance”, IEEE Transactions on Electron Devices, pp 1861-1865, April 2021.
  1107. S-J Chang, C-Y Teng, Y-J Lin, T-M Wu, M-H Lee, T-S Wu, C. Hu, Y-T Tang, Y-C Tseng, “Visualizing Ferroelectric Uniformity of Hf1–xZrxO2 Films Using X-ray Mapping”, ACS Appl. Mater. Interfaces, 29212–29221, June 13, 2021.
  1108. A.J. Tan, Y-H Liao, L-C Wang, N. Shanker, J-H Bae, C. Hu, S. Salahudin,” Ferroelectric HfO2 Memory Transistors With High-κ Interfacial Layer and Write Endurance Exceeding 1010 Cycles”, IEEE Electron Device Letters, July 2021, pp. 994 – 997.
  1109. MY Kao, S Salahuddin, C Hu,”Negative capacitance enables GAA scaling VDD to 0.5 V”, Solid-State Electronics, Volumes 181–182, 1080102021, August 2021.
  1110. H-W Tu, C-C Shih, C-L Lin, M-Z Yu, J-J Lai, J-C Luo, W-B Jian, K. Watanabe, T. Taniguchi, C. Hu, “High field-effect performance and intrinsic scattering in the two-dimensional MoS2 semiconductors”, Applied Surface Science, V. 564, 30 October 2021, 150422G.
  1111. Pahwa, P.Kushwaha, A.Dasgupta, S. Salahuddin, C.Hu, “Compact Modeling of Temperature Effects in FDSOI and FinFET Devices Down to Cryogenic Temperatures”, IEEE Transactions on Electron Devices, p. 4223, Sept. 2021
  1112. S-N Huang, P. Su, C. Hu,”S-Curve Engineering for ON-State Performance Using Anti-Ferroelectric/Ferroelectric Stack Negative-Capacitance FinFET”, IEEE Transactions on Electron Devices, p. 4787, Sept. 2021
  1113. Y-W  Liu, H-W Hu, P-Y Hsieh, H-T Chung, S-J Chang, J-M Hsieh, K-N Chen, C. Hu, “Single-Crystal Islands (SCI) for Monolithic 3-D and Back-End-of-Line FinFET Circuits”, IEEE Transactions on Electron Devices, p.5257, Oct. 2021
  1114. C-T Tung, G. Pahwa, S. Salahuddin, C. Hu, “A Compact Model of Polycrystalline Ferroelectric Capacitor”, IEEE Transactions on Electron Devices, p. 5311, Oct. 2021.
  1115. HT Chung; BJ Shih; CC Yang; NC Lin; PT Huang;….WK Yeh; KN Chen; C Hu,”Ge Single-Crystal-Island (Ge-SCI) Technique and BEOL Ge FinFET Switch Arrays on Top of Si Circuits for Monolithic 3D Voltage Regulators”, IEEE International Electron Devices Meeting (IEDM), December 2021.
  1116. CT Tung; G Pahwa; S Salahuddin; C Hu,”A Compact Model of Metal–Ferroelectric-Insulator–Semiconductor Tunnel Junction”, IEEE Transactions on Electron Devices, pp. 316-318, Feb. 2022.
  1117. M Hoffmann, A J Tan, N Shanker, YH Liao, LC Wang, JH Bae, C Hu, S. Salahuddin,”Fast Read-After-Write and Depolarization Fields in High Endurance n-Type Ferroelectric FETs”, IEEE Electron Device Letters, 30 March 2022.
  1118. S S Cheema, N. Shanke, L-C Wang, C-H Hsu, S-L Hsu, Y-H Liao, …R Ramesh, S Mahapatra, J Ciston, S Datta, M Mohamed, C Hu, S Salahuddin,”Ultrathin ferroic HfO 2-ZrO 2 superlattice gate stack for advanced transistors“, Nature, 604(7904):65-71, Apr. 2022.
  1119. F Zhao, YR Chen, JF Wang, YW Chen, JR Zhou, Y Lin, Y Xing, CW Liu, C Hu,” Engineering Hf0.5Zr0.5O2 Ferroelectric/Anti- Ferroelectric Phases With Oxygen Vacancy and Interface Energy Achieving High Remanent Polarization and Dielectric Constant”, IEEE Electron Device Letters, Volume: 43, Issue: 4, pp. 553-556, April 2022.
  1120. CH Wu, KC Wang, YY Wang, C Hu, CJ Su, TL Wu,” Enhancement of Ferroelectricity in 5 nm Metal-Ferroelectric-Insulator Technologies by Using a Strained TiN Electrode”, Nanomaterials 12(3), 468, January 2022.
  1121. WB Jian, HW Tu, KC Lu, C Hu, K Watanabe, T Taniguchi, “ Investigating interface effects on the single MoS2 flake placed on SiO2 and BN surfaces”, Bulletin of the American Physical Society, March 2022
  1122. Please see full searchable list here: https://scholar.google.com/scholar?hl=en&as_sdt=2005&sciodt=0%2C5&cites=https%3A%2F%2Fpubs.aip.org%2Faip%2Fapl%2Farticle%2F120%2F16%2F162102%2F2833469&scipsc=&q=chenming+Hu&btnG=

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